Nxp B.v.

Hendrik Pieter Hochstenbach

Nicolaas Johannes Anthonius Van Veen

Willem Dirk Van Driel

Rintje Van Der Meulen

Andrea Henricus Maria Van Eck

The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.

Reinforced structure for a stack of layers in a semiconductor component

The present invention relates to a stress buffering package () for a semiconductor component, with a semiconductor substrate (); an I/O pad (), electrically connected to the semiconductor substrate (); a stress buffering element () for absorbing stresses, electrically connected to the I/O pad (); an underbump metallization (), electrically connected to the stress buffering element (); a solder ball (), electrically connected to the underbump metallization (); a metal element () between the solder ball () and the semiconductor substrate (); a passivation layer (), which protects the semiconductor substrate () and the metal element () and which at least partially exposes the I/O pad (); characterized in that a roughness of an interface between the stress buffering element () and the passivation layer () is lower than a roughness of an interface between the metal element () and the passivation layer (). Furthermore the invention relates a method for manufacturing a stress buffering package () for a semiconductor component.

Reduced bottom roughness of stress buffering element of a semiconductor component

The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component.

Stress buffering package for a semiconductor component

An assembly () is provided comprising a first chip () and a second chip () which are interconnected through solder connections. These comprise, at the first chip, an underbump metallization and a solder bump, and, at the second chip, a metallization. In this case the solder bump is provided as a fluid layer with a contact angle of less than 90&#xb0; C., and an intermetallic compound is formed on the basis of the metallization at the second chip, and at least one element of the composition is applied as the solder bump.

Method of assembly and assembly thus made

The electronic device () is a chip-on-chip construction on a lead frame () comprising a heat sink () in an encapsulation (). The first chip () and the second chip () are mutually connected by first conductive interconnections () and the first chip () is connected to the lead frame () by second conductive interconnections () which preferably have a lower reflow temperature than the first conductive interconnections (). By heating the device () the adhesive layer () will first shrink, causing a stress, which will be relaxated by reflowing the second conductive interconnections ().

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Nijmegen, Netherlands

Hendrik Pieter Hochstenbach