Nxp B.v.

Koninklijke Philips Corporation N.v.

Hendricus Joseph Maria Veendrick

Atul Katoch

Evert Seevinck

Rinze Ida Mechtildis Peter Meijer

Victor Zieren

Marcel J Pelgrom

Manish Garg

Kiran Batni Raghavendra Rao

Victor Emmanuel Stephanus Van Dijk

Marcel J M Pelgrom

Leonardus Hendricus Maria Sevat

Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.

Simple and stable reference for IR-drop and supply noise measurements

Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

Flexible CMOS library architecture for leakage power and variability reduction

A sensor () for sensing jitter in a clock signal has a DLL () for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line () having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator () for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

DLL for period jitter measurement

A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module monitor suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module.

Signal integrity self-test architecture

As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Operating long on-chip buses

An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.

Current mode signaling in electronic data processing circuit

An integrated circuit () has a circuit portion () that can be switched to a standby mode through an enable transistor (), which is coupled between an internal power supply line () and an external power supply line (). The enable transistor () is controlled by control circuitry via a control line (). The control line () is coupled to the gates of a first transistor () and a further transistor () of a logic gate (). The substrate of the further transistor () is coupled to a backbias generator (). Consequently, when the enable transistor () is switched off, the further transistor () is enabled and applies a substantial backbias to the gate of the enable transistor (), thus dramatically reducing the leakage current from the circuit portion () through the enable transistor ().

Integrated circuit and battery powered electronic device

The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module supplies the base signal to a first end of the signal conductor for generating an output-signal at a second end of the signal conductor, and wherein, in use, the first module supplies the at least one support signal to the at least one support conductor.

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Eindhoven, Netherlands

Hendricus Joseph Maria Veendrick