National Taiwan University

Industrial Technology Research Institute

Mediatek Corporation

National Science Council

Realtek Semiconductor Inc.

Hen-Wai Tsao

Jing-Shown Wu

Shen-Iuan Liu

Yang-Han Lee

Yu-Lin Shiao

Chieh-Jui Ho

An-Yeu Wu

Hsuan-Jung Su

Jhe-Yi Lin

Yuan-Jyue Chen

Lin-Chieh Chen

Jingshown Wu

Kai-Yuan Jheng

Dong-hong Liu

Ying-Ren Chien

Posen Tseng

Yi-Sing Hsiao

Kun-Tso Chen

Yu-Cheng Fan

Chia-Tseng Chiang

Ronald Y Chang

Jyh-Wai Liao

Lingshown Wu

Miin-Hwa Jiang

Tzong-Bang Yu

The application discloses a method applied in a system. The method includes the following operations: determining a first statistics of a first signal and a second statistics of a second signal according to a power split ratio and a noise level of a relay node; relaying, by the relay node, the first signal according to the power split ratio, the first statistics and the second statistics to generate the second signal; and receiving, by a destination node, the second signal.

Energy harvesting relay communication method and system

The present disclosure relates, according to some embodiments, to a transformer power amplifier that allows for improved Q values and increased efficiency by reducing the capacitance coupling effect between metal layers and/or sidewalls of the same layer through carefully designed conductor structures in primary and secondary loops. A transformer power amplifier comprises a substrate, a conductor, a circular coil, a first amplifier, and a second amplifier, the conductor and the circular coil disposed on the substrate. A circular coil has a first input terminal and a second input terminal, in which the first input terminal and the second input terminal are spaced apart and opposite each other to form an opening. A first amplifier is connected to a first input terminal for receiving a first signal and a second amplifier is connected to a second input terminal for receiving a second signal, wherein the first signal and the second signal are differential signals.

Transformer power amplifier

A transformer hybrid is disclosed. The transformer hybrid comprises a substrate, a first conductor, a second conductor, a first coil, and a second coil. The first conductor includes a first elongate portion having a first side and a second side. The second conductor includes a second elongate portion having a third side and a fourth side, and the orientation of the second conductor intersects with that of the first conductor. The first coil is located near the first side and the third side. The second coil is located near the first side and the fourth side. When the direction of the loading current in the first coil is the same with that in the second coil, the first conductor has an inductive electromotive force. When the direction of the loading current in the first coil is different from that in the second coil, the second conductor has another inductive electromotive force. When phase difference exists between the loading currents, the two loading currents can be resolved to common mode and differential mode, so the inductive electromotive forces can be produced on the both conductors.

Transformer hybrid

A transmitter includes an encoding module, an adaptive hierarchical signal mapping module and a transceiver module. The encoding module receives an input signal and encodes the input signal. The input signal includes data to be transmitted. The adaptive hierarchical signal mapping module modulates the encoded signal according to one or more hierarchical level distance ratios to obtain modulated symbols. The hierarchical level distance ratio defines distances between the modulated symbols. The transceiver module generates a radio frequency signal according to the modulated symbols and transmits the radio frequency signal to an air interface.

Methods for carrier frequency offset detection and compensation and transmitters and receivers utilizing the same

A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.

Spread spectrum clock generator and method for adjusting spread amount

A receiver used for an orthogonal frequency-division multiplexing (OFDM) system is provided. A signal processing device receives an OFDM symbol and processes the OFDM symbol according to the OFDM symbol and a carrier frequency offset compensation coefficient to generate a processed signal. The OFDM symbol includes pilots which have been hierarchically modulated and the processed signal includes the processed pilots. A signal analysis device collects the processed pilots of the processed signal and detects carrier frequency offset to generate the carrier frequency offset compensation coefficient to the signal processing device according to the processed pilots and a plurality of target decision bit error rates. A channel detection module detects a channel response of the processed signal according to the processed pilots and compensates the processed signal to generate an output data.

Methods and receivers of carrier frequency offset detection

A transceiver used for an orthogonal frequency-division multiplexing (OFDM) system is provided, including: a signal processing device for receiving an OFDM symbol and processing the OFDM symbol to generate a processing signal according to the OFDM symbol, wherein the OFDM symbol having pilots which have been hierarchically modulated; a pilot signal analysis device for collecting the processing pilots of the processing signal and demodulating the processing pilots to generate a plurality of levels where one of the plurality of levels comprises a plurality of refinement bits; a degree difference analysis module for generating a plurality of degree differences according to the refinement bits and detecting channel classification according to the degree differences to transmit a channel classification signal; and a channel detection module for generating and transmitting a best modulation indication signal to another transceiver to adjust modulation scheme according to the channel classification signal.

Methods and transceivers for channel classification

An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.

Timing error detector and method thereof

A low complexity acquisition method and a receiver implemented such a method are disclosed. In the present invention, a cyclical shifted-and-combined (CSC) code is generated by intercepting sub-codes from a full code and combining the sub-codes with an equal gain. The CSC code is correlated with a received signal to find a candidate peak. The other candidate peak(s) can be deduced accordingly. Thus, hypotheses can be significantly reduced. A true peak can be easily and rapidly found by verifying the candidate peaks.

Low complexity acquisition method for GNSS

A multilevel LINC transmitter. The multilevel LINC transmitter comprises a multilevel signal component separator, a phase modulator block, and an RF block. The multilevel signal component separator comprises a multilevel scaler and converts a base band signal to constant envelope signals. The phase modulator block is coupled to the multilevel signal component separator. The RF block comprises a plurality of power amplifiers coupled to the phase modulator block and the multilevel scaler and a power combiner coupled to the power amplifiers.

Multilevel LINC transmitter

A self-routing data switching system is disclosed. The data switching system includes a plurality of repetitive switching matrix planes, each of which is electrically connected between a less number of input terminals and a larger number of output terminals, thereby reducing the head-of-line blocking effect. Each switching matrix plane includes a switching element array interconnected between the input ports and the output ports for determining whether the data packet from an input port can be transmitted to a designated output port. The data switching system further includes a plurality of pre-processors to manage the input timing of data packets into the switching matrix array in order to avoid output conflict.

Self-routing data switching system

The present invention provides a method for IC identification. It can be used to identify the origin of the IC design, wherein said IC comprises at least a testing circuit for testing the functional correctness of said IC, and said testing circuit is activated by a testing activation signal. The testing circuit, after receiving a testing signal, will generate a testing result. The identification method comprises the steps of (1). providing an original identification data representing the origin of the IC; (2). transforming the original identification data into a digital identification data; (3). providing an identification circuit for generating the digital identification data, wherein the identification circuit is activated by the testing activation signal, and generates the digital identification data; (4). integrating the identification circuit and the testing circuit into a composite circuit, wherein the composite circuit will be activated by the testing activation signal, receive the testing signal, process the digital identification data from identification circuit and the testing result from the testing circuit, and generate an output signal; (5). inputting the testing activation signal and the testing signal to the composite circuit, and waiting for the output signal; (6). receiving the output signal and processing the output signal to obtain digital identification data; and (7). interpreting the digital identification data to obtain the original identification data.

Method and device for IC identification

A direct digital frequency synthesizer outputting a sine signal is disclosed, comprising an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit, wherein the accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address according to a first clock, the period of the first clock being twice the period of the first MSB of the sample address, to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M MSBs of the symmetric sample address as the first M MSBs of the sine signal. The fine circuit predicts the last N-M LSBs of the sine signal from the last N-M LSBs of the symmetric sample address according to the first M MSBs of the symmetric sample address of the coarse circuit. Then, the sign circuit outputs a sign bit of the sine signal according to a second clock, the period of the second clock being four times that of the period of the first MSB of the symmetric sample address.

Direct digital frequency systhesizer

A differential mode time to digital converter uses a pair of symmetric capacitors and a pair of constant currents to generate two charging curves with the same characteristics. By charging the capacitors at different timings to produce a voltage difference between the capacitors, and then holding and amplifying the voltage difference, a relationship between time and the digital signal is obtained, thereby reducing the effects of temperature on the electronic element and providing a high noise immunity, short conversion time, and high linearity.

Differential mode time to digital converter

A multi-channel carrier wave generator includes a signal source capable of generating a carrier wave having a frequency, a first input-match diode circuit receiving the carrier wave to correspondingly generate a plurality of harmonic waves, a first multi-way power divider electrically connected to the first input-match diode circuit to equally divide the harmonic waves, and a first multi-way filter electrically connected to the first multiple power divider to filter through the harmonic waves. Such a multi-channel carrier wave generator has the advantages of having a simple fabrication procedure, a low cost, and a low phase noise, and capable of providing a stable carrier wave and a good filtering result and of using a lower order bandpass filter.

Growing community of inventors

Taipei, Taiwan

Hen-Wai Tsao