Fairchild Camera and Instrument Corp.

National Semiconductor Corporation

Fairchild Semiconductor Corporation

Fairchild Camera & Instr. Corp.

Hemraj K Hingarh

Madhukar B Vora

Richard E Crippen

Ashok K Kapoor

Michael E Thomas

Charles R Erickson

Dan Wilnai

Peter W Verhofstadt

Robert Moeckel

Richard Pang

Robert Brown

Andres D Asuncion

There is disclosed a structure for self aligned and non-self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.

Thick bus metallization interconnect structure to reduce bus area

A self-aligned silicide base contact structure for a bipolar transistor, and a process for fabricating the structure are disclosed. The structure has four key elements: a base region 36, a polycrystalline silicon emitter contact region 50, a spacer oxide 60 and 62, and a base contact 74 formed of metal silicide. The spacer oxide is an insulator that electrically isolates the side walls of the emitter contact region from the upper surface of the base region. The spacer oxide is a residual amount of oxide that is left on the side walls of the emitter contact region after anisotropic etching is used to remove most of a covering layer of oxide. The metal silicide base contact is created on an exposed upper surface of the base region, and is formed by first depositing a metal layer on the upper surface of the base region, and then heat treating. Where metal and silicon atoms are in contact, such as along the exposed upper surface of the base region, metal silicide forms.

Process for forming self-aligned silicide base contact for bipolar

A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.

Low resistance Schottky diode on polysilicon/metal-silicide

A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

Polycrystalline silicon Schottky diode array

An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Logic structure utilizing polycrystalline silicon Schottky diodes

A microprocessor integrated circuit (50) has a read only memory (ROM) (400) which is X and Y addressible and is word, bit and page oriented. The microprocessor integrated circuit (50) has a main injector bus (602) and a ground return bus (604) with a branch ground bus (608) connected to the ground return bus (604) through a ground-balancing resistor (610) in a data path. The circuit (50) has a register file (82) with registers (622) connected to a local bus (604). The local busses (604) are connected to a main bus (602) through a multiplexer (605). The microprocessor integrated circuit (50) includes a D-type flip-flop circuit (700) with asynchronous clear and preset. A latch dual port random access memory (RAM) circuit (900) is employed in the register file (82) of the microprocessor integrated circuit (50).

Read only memory and decode circuit

A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.2 L clocking pulse input transistors in a T.sup.2 L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.

Combined integrated injection logic and transistor-transistor logic

A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

Method of fabricating self-aligned lateral bipolar transistor utilizing

An integrated injection logic semiconductor structure having a double diffused lateral PNP transistor and an inverted vertical NPN transistor includes an extended region of epitaxial silicon doped N type by introduction of suitable impurity from two separate regions of the semiconductor surface. This extended N type region, which functions as the base of the PNP transistor, allows an adjoining P type region, which in prior art structures served only as the collector, to be utilized as both the collector and the collector contact, thereby reducing the size of the semiconductor structure. Said N type region substantially lessens the series resistance between the base of the NPN transistor and the collector of the PNP transistor, to thereby facilitate manufacture of integrated injection logic circuits operating faster, at higher current levels, and at higher gain than integrated injection logic circuits not utilizing this invention. The extended N type region also facilitates the manufacture of faster multiple collector integrated circuit structures. Additionally, this invention will be useful in fabricating a more compact double diffused lateral transistor structure.

Integrated injection logic with heavily doped injector base self-aligned

A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor. The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory. An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU. Bidirectional three-state logic is used to enable both input and output data, as well as memory addresses, to be transmitted over the same bus thereby simplifying design. In addition, provision is made for coupling an operator console into a system formed around the processor of this invention, thus allowing for a user to interface with the system.

Monolithic microcomputer central processor

A graduated multiple collector structure for inverted vertical bipolar transistors, integrated injection logic devices and the like. The invention increases the gain of more distant collectors toward which current flows laterally past intervening collectors from a base contact, and injector or the like. The series resistance drop and the current loss in the base-emitter junction are compensated for by progressively increasing the effective area of collectors further distant from the source of the base current. Although the graduated collector structure is applicable to a wide variety of semiconductor devices, it is particularly well suited for use in oxide-isolated integrated injection logic gates. A mathematical model is provided which can help to optimize designs incorporating the graduated collector structure.

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San Jose, CA, United States of America

Hemraj K Hingarh