Advanced Micro Devices Corporation

Intel Corporation

Other

Hemmige D Varadarajan

Jeffrey K Greason

Nader Vasseghi

Embodiments of the present invention relate to a voltage clamp circuit including a transistor and a switch. The switch is coupled between a gate of the transistor and a source or a drain of the transistor. Embodiments of the present invention can quickly raise and lower a voltage level supplied to a memory device.

Switchable voltage clamp circuit

In a clocking network with clock distribution in the gigahertz frequencies, low voltage swings are generated and applied instead of full voltage swings. The low voltage swing circuits are differential low voltage swing circuits. True and complement signals are transmitted in the global path, enabling cancellation of common mode noise picked up along the path from the generation point to the destination local ends, where the noise is subtracted from the signals. The low voltage swing circuits include a differential translator/driver, differential repeaters and differential receivers/translators to enable centrally generated low voltage swing clock signals to be distributed throughout the chip and to be faithfully converted to full voltage swing clock signals at the local ends. The input sections of the translator/driver convert a full voltage swing clock signal to a differential pair of low voltage swing clock signals, the differential repeaters are provided to repeat the low voltage swing clock signals to cover the paths up to the respective differential receivers/translators, and the differential receivers/translators convert the low voltage swing clock signals to full voltage swing clock signals.

Circuits for a low swing clocking scheme

Ternary weighted arrangements, for example, arrangements (delay circuits, devices, systems) including a variable delay determined on a ternary basis for use in testing set-up and hold times of a latch.

Arrangements having ternary-weighted parameter stepping

Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a latching sense amp circuit. The latching sense amp circuit is configured in the integrated circuit so that the signals to produce and latch an output signal consist essentially of a precharge pulse and a capture pulse.

Latching sense amplifier

A high frequency input buffer within an integrated circuit that is used to receive a signal from another integrated circuit is described. A preamplifier for use in an input buffer of the integrated circuit is described. The preamplifier includes a differential amplifier with differential input terminals and output terminals. An input data signal and an input reference signal are applied to the differential inputs. The differential output signals are generated in response to the differential input signals and are adapted to be applied to the differential input terminals of an amplifier within the input buffer. An adjusting device within the preamplifier adjusts the differential outputs such that they are in a region of optimum gain for the amplifier.

High frequency input buffer

Three-level ECL or four-level CML are feasible when a low drop current source is incorporated in the series-gated arrangement. The low drop current source consumes less than one-tenth of the voltage span between V.sub.CC and ground. A greater portion of the voltage span between V.sub.CC and ground, up to 4 volts, is therefore reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.

Current source arrangement for three-level emitter-coupled logic and

A dynamic ECL line driver circuit for driving line loads having significant capacitance which includes an input transistor, a reference transistor, a main current source transistor and an emitter follower transistor. The line driver circuit further includes a dynamic current enhancement circuit formed of a buffer portion, a current enhancement portion and a dynamic charge pumping portion. The current enhancement portion includes a current source enhancement transistor and the dynamic charge pumping portion includes a capacitor. The buffer portion is utilized for amplifying and inverting a transient voltage at the collector of the reference transistor. One end of the capacitor is connected to the collector of the reference transistor and the base of the emitter follower transistor, and the other end thereof is coupled to the base of the current source enhancement transistor via the buffer portion. As logic transitions occur at the base of the emitter follower transistor, the transient voltage is impressed upon the base of the current source enhancement transistor so as to speed up the transitions on an output terminal.

Dynamic ECL line driver circuit

A multilevel differential logic gate circuit for generating a plurality of levels of logic includes a single constant current source having its one end connected to a ground potential. The current source has a relatively small voltage drop. A first differential amplifier formed of a pair of first and second transistors have their emitters coupled together and to the other end of the current source to define a first level of logic. A second differential amplifier formed of a pair of third and fourth transistors have their emitters coupled together and to the collector of the first transistor to define a second level of logic. A third differential amplifier formed of a pair of fifth and sixth transistors have their emitters coupled together and to the collector of the third transistor to define a third level of logic. A fourth differential amplifier formed of a pair of seventh and eights transistors have their emitters coupled together and to the collector of the fifth transistor to define a fourth level of logic. The collector of the seventh transistor is connected to a supply potential via a first resistor. The collector of the eighth transistor is connected also to the supply potential via a second resistor.

Multilevel differential ECL/CML gate circuit

In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.

Emitter coupled logic having enhanced speed characteristic for turn-on

A line driver circuit is formed of a driver circuit section and a receiver circuit section. The driver circuit section provide a low impedance drive for charging and discharging quickly a capacitive load. A receiver circuit section includes an output level-shifting transistor which is adapted for translating a voltage at an output node of the driver circuit section to a compatible higher level.

AFL (advanced fast logic) line driver circuit

A standard ECL OR/NOR gate is modified to have a single current source connected to the load current source transistors. The single current source is connected to the emitters of each of the load current source transistors. Switching between the two load current source transistors is accomplished by connecting the base of at least one of the load current transistors to a circuit point that tracks the opposite phase. In one embodiment the base of one of the load current source transistors is connected to the common emitter connections of the input transistors and the reference transistor while the base of the other load current source transistor is connected to a reference voltage source V.sub.BBL having a value intermediate the extreme values which appear on the common emitter connections of the input transistors and the reference transistors. In an alternate embodiment the base of each load current source transistor is connected to a suitable point which tracks the opposite phase outputs of the particular load current source transistor.

ECL Gate with switched load current source

An ECL circuit with a bias circuit is provided which tracks the gain and operating characteristics of other transistors in an integrated circuit. The bias circuit employs the bandgap reference voltage, V.sub.CS, as the power source. By a transistor and resistor network a bias circuit voltage is generated. The bias circuit is useful in providing a bias to the base of a dynamically switchable low drop current source useful in ECL circuits.

ECL Logic circuit with a circuit for dynamically switchable low drop

A dynamic ECL circuit is provided which drives loads having significant capacitance. The dynamic ECL circuit may utilize single level or multiple level logic and may be configured, for example, as an OR/NOR gate. A capacitor is placed between the base of a current source transistor and a circuit point having a logic level complementary to the output connected to the current source. As logic transitions occur within the circuit and are presented on the output, a transient current will be experienced through the capacitor due to the shift in the complementary level thereby momentarily altering the voltage on the base of the current source transistor. The dynamic alteration of base voltage produces a momentary change in the current through the current source transistor which serves to both speed up the high-to-low transition time and the low-to-high transition time on the output line.

Dynamic ECL circuit adapted to drive loads having significant capacitance

In a logic gate which is provided having input transistors each with a collector electrode at a first node (which serves as a signal output node), an emitter electrode at a second node to which all emitters are coupled and a base electrode for receiving binary logic signal input, and further having a load resistor between the first node and a supply voltage coupling, the improvement in that means are provided for controlling the emitter current at the second node in response to voltage on the first node in order to inhibit saturation of the input transistors and to enhance switching speed of the logic gate. The emitter current controlling means may include a current regulating transistor coupled between the second node and a ground reference wherein the base electrode thereof is coupled through a third node to a biasing means coupled to the first node. The current regulating transistor may be a Schottky transistor, that is, a transistor with a Schottky diode coupled between the base electrode and the collector electrode. The biasing means may be a feedback resistor coupled between the first node and the third node. Voltage across the feedback resistor may be clamped to limit voltage range.

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Sunnyvale, CA, United States of America

Hemmige D Varadarajan