Cadence Design Systems, Inc.

Rambus Inc.

Intel Corporation

University of Toronto

Hemesh Yasotharan

Navid Yaghini

Clifford Ting

Robert H Wang

Zhuobin Li

Anthony Chan Carusone

Tony Shuo-Chun Kao

James Guthrie

Robert Wang

Raymond K Tang

Mohammadamin Karami

Multiple voltage amplitudes for an oscillator in a phase-locked loop may be selected to meet various design goals/criteria (e.g., frequency range of operation, jitter, power consumption, etc.). These multiple voltage amplitudes may be stored in a lookup table memory that relates frequency ranges to reference voltages. A reference voltage for a particular oscillator may then be selected and generated. A feedback loop may compare the amplitude output by the oscillator to the reference voltage and adjusts a bias current of the oscillator with the goal of substantially equalizing the oscillator output to the reference voltage.

Oscillator amplitude calibration

A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.

Low jitter clock multiplier circuit and method with arbitrary frequency acquisition

A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Circuit and method to set delay between two periodic signals with unknown phase relationship

Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.

Pulse-amplitude modulated hybrid comparator circuit

An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver. Data rates in excess of 5 Gbps may be realized in monolithic CMOS photodetectors when the signal compensating circuit is properly matched.

Optical receiver with monolithically integrated photodetector

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Toronto, Canada

Hemesh Yasotharan