Nvidia Corporation

Hemayet Hossain

Olivier Giroux

Vyas Venkataraman

Mark Douglas Hummel

Samuel Hammond Duncan

Wishwesh Anil Gandhi

Sanjeev Jain

Larry Robert Dennison

Alexander Toichi Ishii

Nir Haim Arad

Steven E Molnar

Shirish C Gadre

Lacky V Shah

Gregory Muthler

Mark Hairgrove

Michael A Parker

Peter B Holmqvist

George R Lynch

Ronny Krashinsky

Timothy John Purcell

Karan Mehra

James Robertson

David Fontaine

Ze Long

Jeffrey M Smith

Jonathon Stuart Ramsay Evans

Debajit Bhattacharya

Geoffrey Gerfin

Raymond Hoi Man Wong

Piyush Patel

Vikram Sethi

Terje Bergstrom

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

High bandwidth extended memory in a parallel processing system

Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

Thread synchronization across memory synchronization domains

Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Securing memory accesses in a virtualized environment

Distributed address translation in a multi-node interconnect fabric

One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

Control mechanism for fine-tuned cache to backing-store synchronization

Growing community of inventors

San Jose, CA, United States of America

Hemayet Hossain