International Business Machines Corporation

Renesas Electronics Corporation

Stmicroelectronics Gmbh

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Elpis Technologies Inc.

Hemanth Jagannathan

Choonghyun Lee

Ruqiang Bao

Takashi Ando

Paul Charles Jamison

Shogo Mochizuki

Vijay Narayanan

Alexander Reznicek

Sivananda K Kanakasabapathy

Sanjay C Mehta

Christopher Joseph Waskiewicz

Ruilong Xie

Brent A Anderson

Junli Wang

Kangguo Cheng

Vamsi Krishna Paruchuri

Praneet Adusumilli

Jay William Strane

Balasubramanian S Haran

Veeraraghavan S Basker

David V Horak

Dechao Guo

Christian Lavoie

Chun Wing Yeung

Su Chen Fan

Koji Watanabe

Pouya Hashemi

Chun-chen Yeh

Eduard Albert Cartier

Gen Tsutsui

Stefan Schmitz

Devendra K Sadana

Bruce Bennett Doris

Ali Khakifirooz

Heng Wu

Chi-Chun Liu

Unoh Kwon

Ahmet Serkan Ozcan

Siddarth A Krishnan

Barry P Linder

John Rozen

Yann A M Mignot

Hao Tang

Tenko Yamashita

Ghavam G Shahidi

Nicolas J Loubet

Charles W Koburger, Iii

Terence B Hook

Jingyun Zhang

Oscar Van Der Straten

Chun-Chen Yeh

Indira P Seshadri

Johnathan E Faltermeier

Lawrence Alfred Clevenger

Stephen W Bedell

Tak H Ning

Oleg Gluschenkov

Qing Liu

Wenyu Xu

Geng Wang

Zuoguang Liu

Robert Russell Robison

Joel Pereira De Souza

Yann Mignot

Koichi Motoyama

Robert H Dennard

Sufi Zafar

Eric R Miller

Albert Manhee Chu

Cornelius Brown Peethala

Stuart A Sieg

Matthew Warren Copel

Prasanna Khare

Raghuveer Reddy Patlolla

Charan V Surisetty

Pietro Montanini

Chih-Chao Yang

Chen Zhang

Xin Miao

Balasubramanian Pranatharthiharan

Soon-Cheon Seo

Fee Li Lie

Martin Michael Frank

Dirk Pfeiffer

Babar Ali Khan

Griselda Bonilla

Pranita Kulkarni

Robert Daniel Clark

Joshua M Rubin

Dario Leonardo Goldfarb

Muthumanickam Sankarapandian

Roger Allan Quon

Robert Allen Groves

Michael P Belyansky

Lan Yu

Jean Fompeyrine

Tao Li

Stefan Abel

Miaomiao Wang

Hiroshi Sunamura

A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.

Vertical transistor with reduced cell height

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

High density stacked vertical transistor static random access memory structure

VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

Late gate extension

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Looped long channel field-effect transistor

A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor

A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

Self-aligned C-shaped vertical field effect transistor

Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.

Self-aligned uniform bottom spacers for VTFETS

A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

Low-resistance top contact on VTFET

An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Vertical FET with contact to gate above active fin

A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Semiconductor device and method of forming the semiconductor device

A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Forming crossbar and non-crossbar transistors on the same substrate

A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors

A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

Vertical field effect transistor with bottom spacer

A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.

Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection

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Niskayuna, NY, United States of America

Hemanth Jagannathan