Synopsys, Inc.

Hemant Vats

Amit Khanuja

M Sultan M Siddiqui

Shailendra Sharad

Mohammed Sultan Mohiuddin Siddiqui

An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC, . . . , BCn) comprising a first and a second one of the bit cells (BC, BC) having a static random access memory architecture. The first and the second bit cells (BC, BC) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C, C) of the memory cell array (). During a write access to the first bit cell (BC), the first bit cell (BC) undergoes a write operation, whereas the second bit cell (BC) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.

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New Delhi, India

Hemant Vats