Intel Corporation

Hemant V Deshpande

Cory E Weber

Anand S Murthy

Mark Y Liu

Daniel Bourne Aubertine

Oleg Golonzka

Ajay K Sharma

Ashutosh Ashutosh

Mark T Bohr

Sunit Tyagi

Giuseppe Curello

A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Enhanced dislocation stress transistor

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.

Methods of channel stress engineering and structures formed thereby

A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

Strained silicon MOS device with box layer between the source and drain regions

Growing community of inventors

Beaverton, OR, United States of America

Hemant V Deshpande