Intel Corporation

Hemant P Rao

Raymond W Zeng

Mini Goel

Rouhollah Mousavi Iraei

Kiran Pangal

Sanjay Rangan

Shylesh Umapathy

Mase J Taub

Zion S Kwok

Prashant S Damle

Saad Monasa

Phoebe P Yeoh

A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application of a current pulse amplitude profile to the memory cell, wherein the current pulse amplitude profile decreases progressively, encompassing at least four different current pulse amplitudes, the at least four different current pulse amplitudes including a highest current pulse amplitude and a lowest current pulse amplitude.

Apparatus, method and system to reduce memory window latency and read disturb in a memory device for memory operations

A memory device comprising a plurality of memory cells, a memory cell of the plurality of memory cells comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; a first address line and a second address line coupled to the memory cell; and memory controller circuitry to interface with the first address line and the second address line, the memory controller circuitry to encode a state in the memory cell by applying, through the first address line and second address line, a current spike and a programming pulse to the memory cell to cause the PM region to be placed into an amorphous state and the SD region of the memory cell to be placed into a high threshold voltage state.

Spike based programming of a memory cell to reset state

A state may be encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

Encoding additional states in a three-dimensional crosspoint memory architecture

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Cross-point memory read technique to mitigate drift errors

In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

Read algorithms for three-dimensional crosspoint memory architectures

Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

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Albuquerque, NM, United States of America

Hemant P Rao