Applied Materials, Inc.

Matsushita Electric Industrial Co., Ltd.

Hemant P Mungekar

Young Seen Lee

Ganesh Balasubramanian

Manoj Vellaikal

Anchuan Wang

Zhong Qiang Hua

Sanjay G Kamath

Muhammad M Rasheed

Soonam Park

Tom K Cho

Thanh Ngoc Pham

Padmanabhan Krishnaraj

Siqing Lu

Sudhir R Gondhalekar

Jason T Bloking

Bikram Kapoor

Farhan Ahmad

Jin Ho Jeon

Byung Chul Yoon

Yasutoshi Okuno

Peter G Borden

Christopher Sean Olsen

Abdul Aziz Khaja

Li Xu

Michael Johnson

Michael P Stewart

Rongping Wang

Zhijun Jiang

Guomin Mao

Ramesh Gopalan

Hiroshi Yuasa

Anjana M Patel

James Omer L'Heureux

Walter Zygmunt

Yoichi Suzuki

Andreas Neuber

Teryl Pratt

Ryan T Downey

Maxime Cayer

Uwe Paul Haller

Tony H Tong

Jing Wu

Joseph A Van Gompel

Agnieszka Jakubowicz

Rionard Purnawan

Karen Greig

William Pryor

Gino Gerardo Crispieri

John L Koenig

Mike M Huang

The present disclosure relates to systems and methods for detecting anomalies in a semiconductor processing system. According to certain embodiments, one or more external sensors are mounted to a sub-fab component, communicating with the processing system via a communication channel different than a communication channel utilized by the sub-fab component and providing extrinsic sensor data that the sub-fab component is not configured to provide. The extrinsic sensor data may be combined with sensor data from a processing tool of the system and/or intrinsic sensor data of the sub-fab component to form virtual sensor data. In the event the virtual data exceeds or falls below a threshold, an intervention or a maintenance signal is dispatched, and in certain embodiments, an intervention or maintenance action is taken by the system.

Method and system for detecting anomalies in a semiconductor processing system

Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.

Wafer de-chucking detection and arcing prevention

Methods and apparatus for plasma processing are provided herein. For example, apparatus can include a system for plasma processing including a remote plasma source including a supply terminal configured to connect to a power source and an output configured to deliver RF power to a plasma block of the remote plasma source for creating a plasma and a controller configured to control operation of the remote plasma source based on a measured input power at the supply terminal.

Methods and systems for monitoring input power for process control in semiconductor process systems

The present disclosure relate to methods and apparatus for temperature sensing and control during substrate processing. Substrate temperatures during processing, which are difficult to measure directly, may be determined by examination of deposited film properties or by measuring changes in power output over time of the substrate heating apparatus. Temperatures are determined for many substrates during processing, showing how substrate temperatures change over time, and the temperature changes are then used to build models via machine learning techniques. The models are used to adjust heating apparatus setpoints for future processing operations.

Virtual sensor for spatially resolved wafer temperature control

Methods and systems of detection of wafer placement error in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when a wafer placement error is detected. The method&#x2014;is based on measuring a slope of current in an electrostatic chuck (ESC), which is correlated to lack of contact between the wafer and the ESC. Wafer placement detection at an early stage, when a heater and an ESC are being set up, gives the option of stopping the process before high power RF plasma is created.

Wafer placement error detection based on measuring a current through an electrostatic chuck and solution for intervention

Implementations of the present disclosure generally relate to methods for cleaning processing chambers. More specifically, implementations described herein relate to methods for determining processing chamber cleaning endpoints. In some implementations, a 'virtual sensor' for detecting a cleaning endpoint is provided. The 'virtual sensor' is based on monitoring trends of chamber foreline pressure during cleaning of the chamber, which involves converting solid deposited films on the chamber parts into gaseous byproducts by reaction with etchants like fluorine plasma for example. Validity of the &#x201c;virtual sensor&#x201d; has been confirmed by comparing the &#x201c;virtual sensor&#x201d; response with infrared-based optical measurements. In another implementation, methods of accounting for foreline pressure differences due to facility design and foreline clogging over time.

Virtual sensor for chamber cleaning endpoint

A processing chamber and a processing method for processing a substrate in the processing chamber with thermal control are described herein. The method includes heating a first substrate using a heater apparatus during a first processing operation. The heater apparatus has a first setpoint during at least a first portion of the first processing operation. The first substrate is disposed on a substrate support surface of an electrostatic chuck in a processing chamber. The method further includes determining a first parameter change corresponding to a resistivity change in the electrostatic chuck, determining a second setpoint for the heater apparatus based on the first parameter change, and controlling the heater apparatus to the second setpoint.

Processing chamber and method with thermal control

Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel plasma oxidation process to form a passivation film stack on a surface of a solar cell substrate. In one embodiment, the methods include providing a substrate having a first type of doping atom on a back surface of the substrate and a second type of doping atom on a front surface of the substrate, plasma oxidizing the back surface of the substrate to form an oxidation layer thereon, and forming a silicon nitride layer on the oxidation layer.

Passivation process for solar cell fabrication

A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 &#x212b; is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.

Reduction of etch-rate drift in HDP processes

Apparatus and methods for distributing gas in a semiconductor process chamber are provided. In an embodiment, a gas distributor for use in a gas processing chamber comprises a body. The body includes a baffle with a gas deflection surface to divert the flow of a gas from a first direction to a second direction. The gas deflection surface comprises a concave surface. The concave surface comprises at least about 75% of the surface area of the gas deflection surface. The concave surface substantially deflects the gas toward a chamber wall and provides decreased metal atom contamination from the baffle so that season times can be reduced.

Gas baffle and distributor for semiconductor processing chamber

Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process.

Impurity control in HDP-CVD DEP/ETCH/DEP processes

The present invention pertains to methods of depositing low stress/high index multi-layer films on a substrate using an HDP-CVD process. The multi-layer films include two lining layers and a bulk gap-fill layer and the HDP-CVD process employs a reduced substrate bias power during deposition of at least the second lining layer. Deposition of the three layers occurs at reduced deposition temperatures which further reduces the stress of the multi-layer film. The lower stress results in less defectivity which improves the films ability to maintain optical confinement of radiation.

HDP-CVD SiON films for gap-fill

The present invention pertains to methods of depositing low wet etch rate silicon nitride films on substrates using high-density plasma chemical vapor deposition techniques at substrate temperatures below 600&#xb0; C. The method additionally involves the maintenance of a relatively high ratio of nitrogen to silicon in the plasma and a low process pressure.

Low wet etch rate silicon nitride film

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San Jose, CA, United States of America

Hemant P Mungekar