Saankhya Labs Pvt. Ltd.

Tejas Networks Limited

Saankhya Labs Private Limited

Hemant Mallapur

Anindya Saha

Parag Naik

Santhosh Billava

Gururaj Padaki

Sandeep Pendharkar

Sunil Hosur Ramesh

Susmit Kumar Datta

Sunil Hr

Manish Kumar

Viji Rajangam

Smitha Banavikal Math Veerabhadresh

Makarand Kulkami

Venugopal Kolathur

Sudarshan V

Vishwakumara Kayergadde

A virtual Radio Access Network (vRAN) system () for provisioning a virtual Radio Access Network (RAN) that is portable across one or more RAN hardware platforms is provided. The virtual Radio Access Network (vRAN) system () includes a waveform development kit (WDK) (), and a waveform execution environment (). The waveform development kit () defines at least one portable Radio Access Network (RAN) application into a form that is instantiated on a RAN hardware (). The waveform execution environment () (i) monitors real-time schedulable resources in real-time, and (ii) collects one or more statistics and monitors the one or more statistics for network automation. The waveform execution environment () includes a RAN hypervisor () that virtualizes at least one attribute of a spectral resource required to provision the RAN that is portable across at least one hardware platform of the one or more RAN hardware platforms in the RAN hardware.

System and method for provisioning a portable virtual RAN across a plurality of RAN hardware platforms

A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Software defined radio for modulation and demodulation of multiple communication standards

A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.

Mechanism for efficient implementation of software pipelined loops in VLIW processors

An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding

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Bengaluru, India

Hemant Mallapur