Xilinx, Inc.

Hemant Kashyap

Amit Kasat

Tharun Kumar Ksheerasagar

Rohit Bhadana

Mahesh Attarde

Madhusudana Reddy

Pratyush Ranjan

Shantanu Mishra

Uday Kyatham

Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

Circuit design simulation and clock event reduction

Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

Compiler-based generation of transaction accurate models from high-level languages

Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

Data traffic injection for simulation of circuit designs

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Hyderabad Telangana, India

Hemant Kashyap