Sandisk Corporation

National Semiconductor Corporation

Sandisk Technologies Inc.

Micron Technology Incorporated

Sandisk Information Technology (shanghai) Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Kabushiki Kaisha Toshiba

Western Digital Technologies, Inc.

Sandisk Semiconductor (shanghai) Co. Ltd.

Hem P Takiar

Robert C Miller

Chih-Chin Liao

Cheemen Yu

Chin-Tien Chiu

Shrikar Bhagath

Cheeman Yu

Eli Harari

Robert F Wallace

Edwin J Cuellar

Ning Ye

Ken Jian Ming Wang

Han-Shiao Chen

Ranjan J Mathew

Suresh Kumar Upadhyayula

Hong Wan Ng

Jack Chang Chien

Nikhil Vishwanath Kelkar

Chin Hui Chong

Seng Kim Ye

Luu Thanh Nguyen

Peng-Cheng Lin

Joel Bernard Jacobs

Yutaka Nakamura

Robert Andrew Howard

Hiroyuki Yamada

Shaw Wei Lee

Motohide Hatanaka

Kelvin Tan Aik Boo

Michael W Patterson

Hiroyuki Sakamoto

Warren Middlekauff

Gokul Kumar

Michael K Patterson

Chin Tien Chiu

Michael Mostovoy

Ashok S Prabhu

Chien-Ko Liao

Inderjit Singh

Ming Hsun Lee

Robert Dennis Miller

Ning Liu

Venkatesh Ramachandra

Vinayak Ashok Ghatawade

Li Wang

Vani Verma

Matt Peterson

Che-Jung Chang

Enyong Tai

Andre McKenzie

Yan Li

Steven Theodore Sprouse

Hui Liu

Emilio Yero

Jagdish G Belani

Ye Bai

Ka Ian Yung

Zhongli Ji

Gursharan Singh

Shih-Ping Fan-chiang

Chi-Chin Liao

Ong King Hoo

Java Zhu

Robert E Hilton

Hee Jhin Kim

Jack Chang-Chien

C C Liao

Lei Shi

Tong Zhang

Jaime A Bayan

Shahram Mostafazadeh

Ken Pham

Joseph O Smith

Wesley G Brewer

Zhong Lu

Peter Howard Spalding

Ting Liu

Seth Robert Sanders

Yangming Liu

Binbin Zheng

Shineng Ma

Peng Chen

Randy Hsiao-Yu Lo

Weiting Jiang

Timothy L Garverick

Kaiyou Qian

George F Reyling, Jr

King Hoo Ong

Christopher G Quentin

Fred Drummond

Cade Murray

Divyesh P Shah

Fisher Yu

Nandha Kumar Mohanraj

James L Crozier

Kuan Luen Chen

Uli H Hegel

Thomas George

A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Overlapping die stacks for NAND package architecture

An apparatus includes a primary layer of a substrate. The apparatus includes a secondary layer of the substrate having a first open area that extends through the secondary layer to an inner layer of the substrate. The apparatus includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes first component bond pads that are disposed on the inner layer and that are exposed via the first open area of the secondary layer.

Surface mount device bonded to an inner layer of a multi-layer substrate

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods

Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.

Systems and methods for reducing the size of a semiconductor assembly

An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer

Overlapping die stacks for nand package architecture

An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Semiconductor devices with multiple substrates and die stacks

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.

A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

Semiconductor package and method of fabricating semiconductor package

A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Manufacturing process for separating logic and memory array

A substrate semiconductor layer is attached to a carrier substrate through a sacrificial bonding material layer. A plurality of semiconductor dies included within continuous material layers are formed on a front side of the substrate semiconductor layer. Each of the continuous material layers continuously extends over areas of the plurality of semiconductor dies. A plurality of dicing channels is formed between neighboring pairs among the plurality of semiconductor dies by anisotropically etching portions of the continuous material layers located between neighboring pairs of semiconductor dies. The plurality of dicing channels extends to a top surface of the sacrificial bonding material layer. The sacrificial bonding material layer is removed selective to materials of surface portions of the plurality of semiconductor dies using an isotropic etch process. The plurality of semiconductor dies is singulated from one another upon removal of the sacrificial bonding material layer.

Semiconductor die singulation using a sacrificial bonding material layer and an anisotropic channel etch

Growing community of inventors

Fremont, CA, United States of America

Hem P Takiar