Lucent Technologies Inc.

Agere Systems Guardian Corp.

Nexplanar Corporation

Agere Systems Inc.

Neopad Technologies Corporation

Hem M Vaidya

Pradip Kumar Roy

Sailesh Mansinh Merchant

Sundar Srinivasan Chetlur

Samir Chaudhry

Manish Deopura

Isik C Kizilyalli

Sudhanshu Misra

Nace Layadi

David Charles Brady

James Theodore Clemens

Arun Kumar Nanda

Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs

Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous grooves, double spiral grooves, and multiple overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

A NMOSFET semiconductor device is formed having an LDD structure by simultaneous co-implantation of arsenic and phosphorous to form an N&minus; layer. The co-implantation is performed subsequent to the formation of the gate structure and a thin (100 &angst;-300 &angst;) gate spacer but prior to the implantation of a highly doped N&plus; source/drain.

Method of forming semiconductor device with LDD structure

A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method

The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same

Polishing fluid polishing method semiconductor device and semiconductor device fabrication method

An integrated circuit capacitor includes a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line.

Integrated circuit capacitor including anchored plugs

An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.

Integrated circuit capacitor including tapered plug

A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.

Method of making integrated circuit capacitor including tapered plug

Methods of manufacturing a semiconductor device. One method includes the steps of: (1) providing a substrate over which is to be deposited a metal silicide layer having a stoichiometric ratio within a desired range, (2) providing a target composed of a metal silicide, the target subject to degradation by reason of use, (3) sputtering atoms from the target to form the metal silicide layer over the substrate, the stoichiometric ratio subject to being without the desired range by reason of the degradation of the target and (4) depositing a predetermined amount of silicon on the metal silicide layer to return the stoichiometric ratio to within the desired range, a useful life of the target thereby increased.

Method of manufacturing semiconductor devices having improved polycide

A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. The electrodes and dielectric layers of the capacitor are formed so that they line the second trench.

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Orlando, FL, United States of America

Hem M Vaidya