Intel Corporation

Hem Doshi

Lakshminarayana Pappu

Suketu U Bhatt

Timothy J Callahan

Hooi Kar Loo

Baruch Schnarch

Efraim Rotem

Nir Rosenzweig

Shaun M Conrad

Yoni Aizik

Michael J Norris

Tomer Ziv

Esfir Natanzon

Arik Gihon

Christopher J Lake

Yevgeni Sabin

Nimrod Angel

Ido Melamed

Ruchira K Liyanage

Yoav Ben-Raphael

Chen Ranel

Natanel Abitan

Kai Chen

Anand Raju

Reena Patel

Vijay Degalahal

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactions onto the device fabric. Other related embodiments are disclosed.

Innovative high speed serial controller testing

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing a virtual device observation and debug network for high speed serial IOS

In one embodiment, a request may be received to load firmware on a microcontroller of a device. A firmware transfer may be initiated to load the firmware on the microcontroller. Data traffic may be monitored at one or more locations on a communication path associated with the firmware transfer. It may be determined whether the data traffic matches a digital fingerprint associated with the firmware.

Firmware fingerprinting based on data monitored during firmware loading

Dead cycles are removed from an upstream side of a data communications bus. In one example, data symbols are received on clock cycles from lanes of a peripheral device bus having dead cycles. The data symbols are sent upstream on the clock cycles. The start of a packet in the received data symbols is detected and the sending of the data symbols is stalled before sending the start of the packet until additional cycles of data are written into a buffer. Logical idle symbols are sent upstream in place of the data during the stalling. The start of the packet sent after the additional cycles of data are read into the buffer. When a dead cycle is detected during the packet, then a buffered cycle of data is sent upstream during the dead cycle.

Removing upstream dead cycles in a data communications bus

According to one embodiment, an apparatus includes a transaction data storage to store transaction data to be transmitted over an interconnect of a data processing system, a transaction buffer coupled to the transaction data storage to buffer at least a portion of the transaction data, and a transaction logic coupled to the transaction data storage and the transaction buffer to transmit a request (REQ) signal to an arbiter associated with the interconnect in response to first transaction data that becomes available in the transaction data storage, in response to a grant (GNT) signal received from the arbiter, retrieve second transaction data from the transaction buffer and transmit the second transaction data onto the interconnect, and refill the transaction buffer with third transaction data retrieved from the transaction data storage after the second transaction data has been transmitted onto the interconnect.

Latency agnostic transaction buffer for request-grant protocols

Growing community of inventors

Folsom, CA, United States of America

Hem Doshi