Xilinx, Inc.

Hem C Neema

Sonal Santan

Kumar Deepak

Alexandre Isoard

Lin-Ya Yu

Stephen P Rozum

Valeria Mihalache

Soren T Soe

David K Liddell

Nabeel Shirazi

Chi Bun Chan

Khang Kim Dao

Kyle Corbett

Saikat Bandyopadhyay

Jimmy Zhenming Wang

Ishita Ghosh

Fangqing Du

Nik Cimino

Xin Jin

Ralph D Wittig

Sundararajarao Mohan

Paul R Schumacher

L James Hwang

Dan Liu

Sheng Wang

Luciano Lavagno

Pramod Chandraiah

Chandrasekhar S Thyamagondlu

Ravi Nagarajarao Kurlagunda

Jason Villarreal

Satish R Ganesan

Roger Ng

Julian M Kain

Ryan Radjabi

David Roth

Yi Wang

Kenneth Chan

Yenpang Lin

Alain Darte

Anurag Dubey

Christopher J Case

Lizhi Hou

Sandeep S Deshpande

Bin Ochotta

Umang Parekh

Idris I Tarwala

Sarabjeet Singh

Lixin Huang

Thomas Bollaert

Chaosheng Shi

Karen Xie

Khang K Dao

Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.

Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis

Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.

Inter-kernel dataflow analysis and deadlock detection

Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

Early detection of sequential access violations for high level synthesis

Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Static and automatic inference of inter-basic block burst transfers for high-level synthesis

A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.

Unified container for hardware and software binaries

An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

Data-driven platform characteristics capture and discovery for hardware accelerators

High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

High-level synthesis implementation of data structures in hardware

A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

High-level synthesis vector library for single-instruction multiple data programming and electronic system design

Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation. Permitting multiple users to directly configure and use the hardware card may present a security risk. To mitigate this risk, the embodiments herein describe techniques for validating encrypted binary files.

Enabling integrity and authenticity of design data

A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Streaming platform flow and architecture for an integrated circuit

Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.

Updating firmware for programmable integrated circuits in computing environments

An integrated circuit (IC) may include a scheduler for hardware acceleration. The scheduler may include a command queue having a plurality of slots and configured to store commands offloaded from a host processor for execution by compute units of the IC. The scheduler may include a status register having bit locations corresponding to the slots of the command queue. The scheduler may also include a controller coupled to the command queue and the status register. The controller may be configured to schedule the compute units of the IC to execute the commands stored in the slots of the command queue and update the bit locations of the status register to indicate which commands from the command queue are finished executing.

Embedded scheduling of hardware resources for hardware acceleration

A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

Unified address space for multiple hardware accelerators using dedicated low latency links

Embodiments herein describe reconfigurable integrated circuits (ICs) which include programmable logic that can be configured to perform a user task. In one embodiment, the programmable logic is configured as an accelerator. The user may want to gather debug data or profiling data when executing the accelerator. Rather than using debug/profile circuitry disposed in a static region of the IC, the user can provide preferences to a linker which then dynamically configures debug/profile circuitry in a dynamic region of the IC. That is, based on user preferences, the linker can generate customized debug/profile circuitry for monitoring the performance of the accelerator. In one embodiment, the debug/profile circuitry is implemented in the dynamic region of the IC and is tailored to user preferences rather than relying on static, or fixed, debug/profile circuitry. Moreover, the user can retrieve the debug/profiling data on demand using a call back and a device driver.

Customizable debug and profile monitoring of reconfigurable systems

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San Jose, CA, United States of America

Hem C Neema