Siemens Aktiengesellschaft

Helmuth Treichel

Konrad Hieber

Oswald Spindler

Heinrich Koerner

Bernhard Neureither

Zvonimir Gabric

Alexander Gschwandtner

Frank S Becker

Peter Kuecher

Rainer Braun

Thomas Kruck

Jasper Von Tomkewitsch

Submicron contact holes in semiconductor bodies are metalized in a single operation. A titanium-rich layer is first deposited, which is followed by a low-resistance TiSi.sub.2 layer. The two layers are thus deposited in one contiguous CVD process inside a single CVD chamber.

Method for metallizing submicron contact holes in semiconductor bodies

The method of the present invention provides in a simple manner, the deposition of boron nitride layers with microcrystalline cubic structure which are suitable as insulating layers in VLSI-circuits, as mask membranes in x-ray lithography, as well as coating hard substances. Due to the use of excited starting substances that already contain boron and nitrogen in one molecule and are preferably liquid or solid, and the use of a plasma-CVD-method, the method can be performed using in temperatures of below 500.degree. C. The excitation of the starting substance proceeds preferably in inductive or capacitative fashion in a hollow cathode.

Method for manufacturing microcrystalline cubic boron-nitride-layers

Methods and apparatus for producing conductive layers or structures for VLSI circuits. In a method for producing conductive layers or structures for VLSI circuits, at least two method stages are implemented in direct succession in different chambers of a high-vacuum system without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the method stages produces noticeably improved layer properties and enables particularly simple and reliable multi-stage methods for producing conductive layers that promote a multi-layer wiring on the semiconductor substrate. An apparatus for implementing the method has a plurality of high-vacuum process chambers, at least one high-vacuum distributor chamber connecting the process chambers and of at least two high-vacuum supply chambers for semiconductor substrates.

Method and apparatus for producing conductive layers or structures for

In the ozone-activated deposition of insulating layers, different growth rates can be achieved on differently constituted surfaces. When the surfaces of the structured silicon substrates lying at different levels are differently constituted or, respectively, are intentionally varied such that the SiO.sub.2 insulating layer grows more slowly on the higher surfaces than on the more deeply disposed surfaces and when deposition is carried out until the surfaces of the rapidly growing and slowly growing layer regions form a step-free, planar level, a local and global planarization is achieved.

Method for locally and globally planarizing chemical vapor deposition of

To create silicon boronitride layers that are utilized as intermetallization layers and/or as final passivation layers, the present invention provides a method wherein fluid initial compounds that already molecularly contain a part of the target composition of the silicon boronitride layer to be produced are utilized, and deposited through chemical vapor deposition in an alternating electromagnetic field. The silicon boronitride layers produced in this fashion have a dielectric constant whose value is below 4 .epsilon..sub.o and are distinguished by good insulating and blocking properties and by a high break down strength.

Method for producing silicon boronitride layers

A method of producing a defined arsenic doping in silicon semiconductor substrates is provided. Preferably, the arsenic doping is produced in the sidewalls and floors of trenches having high aspect ratio which are etched into the substrates. An arseno-silicate glass layer is deposited into these trenches to be used as a diffusion source, the glass layer being removed after the diffusion. The arseno-silicate glass layer is deposited by thermal decomposition from the vapor phase of tetraethylortho silicate Si)OC.sub.2 H.sub.5).sub.4 and triethylarsenate AsO(OC.sub.2 H.sub.5).sub.3. A steep and reproducible doping profile having constant, maximum penetration depth and high arsenic concentration in the substrate surface which is needed for VLSI semiconductor circuits is obtained through the process of the present invention.

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Augsburg, Germany

Helmuth Treichel