Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag I.in.

Helmut Wurzer

Martin Schrems

Reinhard Mahnkopf

Lothar Bauch

Dirk Drescher

Helmut Horst Tews

Robert Feurle

Gerhard Kunkel

Wolfram Karcher

Anke Krasemann

Hermann Sachse

Thomas Huttner

Thomas Pompl

Volker Penka

Ina Voigt

Schrems Martin

Guiseppe Curello

A photolithographic mask having half tone main features and perpendicular half tone assist features. One embodiment provides for the exposure of radiation-sensitive resist layers on semiconductor substrates. The mask has at least one radiation-transmissive substrate and at least one half-tone layer. The half-tone layer is used to provide main features, the main features being formed in such a way that the pattern formed by the main features is transferred into the resist layer when irradiated, and the half-tone layer is also used to provide assist features, the assist features being formed substantially perpendicular to the main features in such a way that the pattern formed by the assist features is not transferred into the resist layer when irradiated.

Photolithographic mask having half tone main features and perpendicular half tone assist features

A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called 'tilting' of the structures under non-optimum focus conditions is significantly reduced or completely avoided.

Photolithographic mask

A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is characterized in that the relative premittivity of the tungsten oxide layer is higher than 50.

Process for fabrication of a semiconductor component having a tungsten oxide layer

A semiconductor configuration has a base layer made of semiconductor material and formed, in particular, by a substrate. An insulation layer is arranged above the base layer, and a layer made of monocrystalline silicon adjoins the insulation layer. A passivating substance is present, with the formation of Si&#x2014;X bonds, in the region of the interface between the insulation layer and the monocrystalline silicon layer. The bond energy of the Si&#x2014;X bond is greater than the bond energy of an Si&#x2014;H bond.

SOI semiconductor configuration and method of fabricating the same

A trench capacitor for use in a semiconductor memory cell is formed in a substrate and includes a trench having an upper region and a lower region. An insulation collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A dielectric layer, which is formed from tungsten oxide, serves as a capacitor dielectric. A conductive trench filling, which is filled into the trench, is formed from silicon or a tungsten-containing material such as tungsten, tungsten silicide or tungsten nitride.

Trench capacitor and method for fabricating the same

A method of fabricating a barrier layer includes oxidizing a silicon-containing substrate to form a substrate oxide layer on the surface of the substrate, producing an oxygen-impervious layer at an interface between the substrate oxide layer and the substrate, and etching the substrate oxide layer until the underlying oxygen-impervious layer is uncovered.

Method for fabricating a barrier layer

Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits having both a memory region and a logic region are fabricated either with different dopings for pMOS and nMOS transistors in the logic region (dual work function) or with a common source/drain electode in the memory region (borderless contact). In the latter case, all the transistors of the semiconductor circuit receive the same gate doping. A method is proposed by which it is possible to realize dual work function and borderless contact on a semiconductor substrate simultaneously in a simple manner.

Method for fabricating an integrated semiconductor circuit

A method for setting the threshold voltage of a MOS transistor having a gate composed of polysilicon includes the step of implanting germanium ions into the gate composed of polysilicon in order to change the work function of the gate.

Method for setting the threshold voltage of a MOS transistor

A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the heavily doped or siliconized zone in the vicinity of a contact hole before a titanium layer is applied to the heavily doped or siliconized zone in the vicinity of the contact hole. As a result of the fluorine, any oxide layers present in the contact hole region can be broken up by less titanium, with the result that a thinner titanium layer is sufficient. In addition, the formation of titanium silicide in the contact hole is promoted.

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Dresden, Germany

Helmut Wurzer