Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh

Infineon Ag

Helmut Strack

Hans-Joachim Schulze

Anton Mauder

Gerald Deboy

Franz Hirler

Jenoe Tihanyi

Hans-Joerg Timme

Dirk Ahlers

Michael Rueb

Ralf Otremba

Hans Martin Weber

Armin Willmeroth

Josef Hoeglauer

Frank Dieter Pfirsch

Hans Weber

Franz-Josef Niedernostheide

Jeno Tihanyi

Jens-Peer Stengl

Helmut Gassel

Horst Theuss

Wolfgang Werner

Xaver Schloegel

Jens Peter Konrath

Wolfgang Lehnert

Klemens Pruegl

Marko Lemke

Adolf Koller

Rudolf Berger

Stefan Sedlmaier

Andre Rainer Stegner

Reinhard Ploss

Holger Kapels

Gerhard Miller

Dieter Kaiser

Kurt Sorschag

Felix Braun

Marcel Heller

Daniel Sarlette

Rainer Winkler

Ingo Meusel

Thorsten Meyer

Johannes Georg Laven

Thoralf Kautzsch

Werner Schustereder

Peter Irsigler

Markus Brunnbauer

Frank Hille

Holger Schulze

Reiner Barthelmess

Carsten Schaeffer

Elmar Falck

Wolfgang Friza

Wolfgang Jantscher

Michael Stoisiek

Helmut Herberg

Werner Kroeninger

Heinrich Brunner

Alfred Porst

Ottmar Geitner

Frank Kahlmann

Josef Georg Bauer

Werner Kanert

Joost Larik

Josef Schwaiger

Jenö Tihanyi

Helmut Hertrich

Gottfried Schuh

Jens P Stengl

Herbert Pairitsch

Joachim Burtscher

Ludwig Schneider

Charles-Wee-Ming Lee

Michael R&uuml;b

Oliver H&auml;berlen

Heinrich Geiger

Horst Schmid

Vytla Rajeev Krishna

Charles Lee

A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Zdefects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Zdefects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.

Semiconductor device having a silicon carbide drift zone over a silicon carbide field stop zone

A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.

Method of manufacturing a semiconductor device and semiconductor device

One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes irradiating the semiconductor body via the one side with further particles at least in the region containing the dopant particles. The method finally includes carrying out a thermal treatment by means of which the semiconductor body is heated, at least in the region containing the dopant particles, to a predetermined temperature in order to activate the implanted dopant particles, said temperature being less than 700&#xb0; C.

Method for fabricating a doped zone in a semiconductor body

A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

Method for producing a doped semiconductor layer

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.

Methods for manufacturing semiconductor devices

In accordance with one component, a power field effect transistor is proposed, including a substrate, a channel, a gate electrode, and a gate insulator. The gate insulator is arranged at least partly between the gate electrode and the channel and includes a material having a hysteresis with respect to its polarization, such that a switching state of the transistor produced by a voltage applied to the gate electrode is maintained after the voltage has been switched off. Furthermore, a half-bridge circuit is proposed, including a high-side transistor in accordance with the construction according to the disclosure, and a low-side transistor, and also methods and circuits for driving.

Field effect semiconductor component and methods for operating and producing it

A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.

Method for manufacturing a semiconductor device

One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions.

Semiconductor body with a buried material layer and method

A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a trench which extends from the main surface into the first n-type semiconductor region, and forming a dielectric layer having fixed negative charges on a surface of the trench, by performing at least one atomic layer deposition using an organometallic precursor.

Method for forming a power semiconductor device

A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.

Method for fabricating a trench structure, and a semiconductor arrangement comprising a trench structure

A method of manufacturing a semiconductor device includes forming a charge compensation device structure in a semiconductor substrate. The method further includes measuring a value of an electric characteristic related to the charge compensation device. At least one of proton irradiation and annealing parameters are adjusted based on the measured value. Based on the at least one of the adjusted proton irradiation and annealing parameters the semiconductor substrate is irradiated with protons, and thereafter, the semiconductor substrate is annealed.

Method of manufacturing a semiconductor device including proton irradiation and semiconductor device including charge compensation structure

A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Method for producing a semiconductor

A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.

Method for producing a semiconductor layer

A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Power semiconductor device and a method for forming a semiconductor device

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Munich, Germany

Helmut Strack