Infineon Technologies Ag

Qimonda Ag

Infineon Technologies North America Corp.

Helmut Seitz

Manfred Menke

Wolfgang Hokenmaier

Josef Schnell

Harald Lorenz

A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage on a supply voltage line and a control circuit which is connected to the supply source for switching on and off the supply source. The control circuit can itself be switched off and regularly switched on again, wherein the control circuit includes a control unit in order to switch the supply source on and off in such a way that the internal supply voltage on the supply voltage line differs essentially by no more than a limit value as a result of capacitive charge storage.

Voltage supply circuit, in particular for a DRAM memory circuit, as well as a method for controlling a supply source

A memory component includes at least one memory bank array, a DQ region, a clock tree, and a voltage generator. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it during a read operation. The clock tree is coupled to the DQ region and is configured for driving data during the read operation. The voltage generator is coupled to at least some components of the clock tree in order to provide at least some of the components of the clock tree with an increased voltage.

Boosted clock circuit for semiconductor memory

An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an external interface. The apparatus includes a switch, coupled to a current source and to the pad receiving signals from the external interface. The switch outputs one of the signals from the current source or the pad in response to a switch control signal. An oscillator is coupled to the switch and generates the refresh operation pulses in response to the output from the switch.

Method and apparatus for an oscillator within a memory device

A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the generator system a state control signal that commands the generators to be in an active state or a standby state, and a self-refresh oscillator that generates a self-refresh clock signal having a period suitable to refresh memory cells of the memory device. The controller uses the self-refresh clock signal to delay transitions of the state control signal from the active state to the standby state relative to corresponding state changes of at least one external signal received by the memory device.

Methods and apparatus for implementing standby mode in a random access memory

A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply voltage and a reference voltage. The voltage source is configured to provide an output voltage out of the boosted supply voltage and based on the reference voltage.

Random access memory having voltage provided out of boosted supply voltage

A memory includes a power-up circuit configured to increase a first voltage to a first value with a second voltage tied to ground, reduce the first voltage from the first value to a second value with the second voltage floating to reduce the second voltage through a parasitic coupling capacitance, and pump the second voltage to reduce the second voltage to a third value with the first voltage less than the second value.

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Essex Junction, VT, United States of America

Helmut Seitz