International Business Machines Corporation

Helmut Schettler

Thomas Ludwig

Otto M Wagner

Rainer Zuhlke

Rainer Stahl

Volker Kreuter

Juergen Pille

Erich Klink

Werner O Haug

Rainer Zuehlke

Peter Gansauge

Kurt Pollmann

Karl E Kroll

Gunther W Kotzle

Karl-Eugen Kroell

Gene J Gaudenzi

Thomas-Michael Winkel

Arnold Blum

Allan Harvey Dansky

Herve L Beranger

Willi Recktenwald

Kenneth A Van Goor

Dennis C Reedy

Edward F Culican

Philip E Pritzlaff, Jr

Heinz G Horbach

Ewald E Stadler

Hans Schumacher

Harald W Gruber

Rudolf Brosch

Martine M Savalle

Klaus Klein

Uwe Schulz

Wolf-Dieter Lohlein

Donald Dunbar Howard

Horst Krumm

Eddehard F Miersch

The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends.

Measurement arrangement for determining the characteristic line parameters by measuring scattering parameters

An improved hardware circuit simulation method in particular for history-dependent and cyclic operation-sensitive hardware circuits, like SOI-type hardware, checks for correct cyclic boundary conditions by performing a first run of a DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed before being simulated in vain with a great amount of work and computing time. A transient simulation can be appended for automated correction of dynamic errors.

Automatic check for cyclic operating conditions for SOI circuit simulation

A press-fit integrated chip package is provided comprising a laminate base structure having plated through holes for introducing press-fit elements, and a laminate cover structure providing very fine conducting paths and having a top mounting plane for mounting chips.

Press-fit chip package

An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.

SOI transistor with body contact and method of forming same

CMOS integrated semiconductor circuit

A module containing an electronic package provides a housing for cooling and protecting the electronic package. A top metal shell and a bottom metal shell form a common cavity in which the package is embedded without touching the inner walls of the cavity. A flexible thermally conductive foil is fixed to each of the shells. The foil is adjustable to the surface of the package and is isolated from electrically conductive parts of the package. A cooling liquid fills the gaps between the metal shells and the foils. Flexible isolated circuit means connect the package to the outside of the housing, balancing means balance pressure and volume between the shells, and further means firmly hold together the housing.

Module for electronic package

A method for making an integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

Method for manufacturing an integrated circuit chip bump electrode using

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

Integrated circuit package

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

An integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer, further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

Integrated circuit substrate with contacts thereon for a packaging

The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesired noise voltage during switching. The present invention achieves this end by using a control circuit composed of a differential amplifier which has one input fed from the junction of an impedance resistor and a transistor that simulate the power stage transistor in the power amplifier being switched. This control circuit provides control voltage outputs to power control transistors which are connected to and control the speed of the power stage transistors used to change and discharge the capcitively loaded line.

Circuit for increasing the output impedance of an amplifier

For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

Method for physical VLSI-chip design

A static memory cell comprising a pair of cross-coupled transistors and a bit line driver/isolation stage configured as an inverter disposed between one node of the cross-coupled transistors and a read-select transistor. The cell is accessed through a bus which includes a read bit line and a write bit line, the word line being divided into a write word line and a read word line.

Non-clocked static memory cell

A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

Method for digital slope control of output signals of power amplifiers

A small signal swing line driver, that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver includes a clamp connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver. The driver also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver and thereafter coupled onto quiet lines.

Growing community of inventors

Dettenhausen, Germany

Helmut Schettler