Quickturn Design Systems, Inc.

International Business Machines Corporation

Quicktum Design Systems, Inc.

Helmut Roth

William F Beausoleil

Tak-kwong Ng

Peter Tannenbaum

Lawrence A Thomas

Norton J Tomassetti

R Bryan Cook

N James Tomassetti

Roy Glenn Musselman

Wilm Ernst Donath

A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.

High speed software driven emulator comprised of a plurality of emulation processors with improved board-to-board interconnection cable length identification system

A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.

High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation

Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of 'cascade' connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Clustered processors in an emulation engine

In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256&#xd7;8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory

A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a 'done' signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory

A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

High speed software driven emulator comprised of a plurality of emulation processors with an improved maintenance bus that streams data at high speed

In an emulation system, the emulation processors are grouped in clusters which are capable of interchanging information between both input memory stacks and data memory stacks associated with each of the processor elements. This capability significantly enhances the performance of emulation engines and, in particular, it provides a mechanism for emulation of memory array elements in computer systems in a more efficient and faster manner.

Tightly coupled emulation processors

A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted circuit form provides the same simulation/emulation results as would have been obtained with the original logic circuit. The method operates with multi-phase logic designs comprised of gate circuits using multi-phase clocking of the type commonly packaged in semiconductor chips. The method converts such multi-phase logic designs into a single-phase circuit form, which is presented to the computer for simulation/emulation that provides the same results as the multi-phase logic design but at a much faster speed. The method is presented with a multi-phase logic design containing flip-flops as the internal storage circuits. The method effectively retains the storage circuits found in a multi-phase logic design and replicates its logic blocks providing multiple phase outputs. Then the storage circuits are reconnected to the original and replicated logic blocks in a manner that enables a single clock cycle to operate the converted logic design to simulate/emulate the same results in the storage circuits, as if the original multi-phase logic design were being simulated or emulated, but at a much faster speed.

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Hopewell Junction, NY, United States of America

Helmut Roth