Intel Corporation

Intel Mobile Communications Gmbh

Lantiq Deutschland Gmbh

Infineon Technologies Ag

Lantiq Beteiligungs Gmbh & Co. Kg

Intel IP Corporation

Helmut Reinig

Vladimir Todorov

Patrik Eder

Soeren Sonntag

Simona Bernardi

Todor M Mladenov

Pradeep R Kumar

Stefan Linz

Sören Sonntag

Alberto Ghiribaldi

Andre Oliver Richter

Amit Badole

Abhiram Anantharamu

Christian Klein

Arumugam Vijayaraman

An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.

Distributed timestamping in networks

An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.

Trace network used as a configuration network

Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.

Control and data multiplexing

A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.

Circuit arrangement, network-on-chip and method for transmitting information

An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.

Arbiter device and arbitration method

A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.

System having trace resources

Apparatuses and methods relate to tracing exchanges of a plurality of signals, including requests and responses, made between a master device and a slave device of the system on chip. The apparatuses and methods further relate to tracking the number of requests and the number of responses made before and after tracing is activated for determining which responses to trace after tracing is activated and for determining which remaining number of responses to trace after tracing is deactivated.

Method and apparatus for interconnect tracing and monitoring in a system on chip

A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Selectable access rates in a memory and memory communication system

Embodiments related to arbitration are described and depicted.

Growing community of inventors

Isen, Germany

Helmut Reinig