International Business Machines Corporation

Helmut Kohler

Norbert Schumacher

Ingemar Holm

Francois Abel

Gottfried Andreas Goldrian

Gerhard Zilles

Erich Klink

Thomas G Koehler

Gilles Gervais

Harald Pross

Joerg Kayser

Peter Mannherz

Andreas Eisenhoffer

Harald Fischer

According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.

Retrieving odd net topology in hierarchical circuit designs

A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch

A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Combined and data compressed FIFO based arbitration for a non-blocking switch

The present invention relates to a method and system for testing error detection programs dedicated for detecting hardware failures in a computer system, in which error case patterns comprising stimuli values are generated and response patterns to the hardware are evaluated. In order to develop and debug such error detection programs already at an early phase during hardware development it is proposed to feed a simulation model () of said hardware with said error patterns, and after running said model, evaluating () the model response patterns generated by the simulation model and comparing the response patterns with those expected as a result of the error detection program.

IML-stream generated error insertion / FRU isolation

Checking data integrity in buffered data transmission

A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

Method and apparatus for checking the address and contents of a memory

The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.

High density semiconductor memory module using split finger lead frame

A programmable logic cell, compatible with LSSD (Level Sensitive Scan Design) technique, is described whose internal logic function can be initially loaded from an EPROM or external processor. The output or contents of one cell can be connected to another cell to alter the logic operation of the second cell even while this second cell is in operation. The cells can be connected together to form a neural network.

Growing community of inventors

Moensheim, Germany

Helmut Kohler