Siemens Aktiengesellschaft

Infineon Technologies Ag

Helmut Klose

Emmerich Bertagnolli

Thomas Scheiter

Markus Biebl

Reinhard J Stengl

Thomas Meister

Hans-Willi Meul

Werner Weber

Christofer Hierold

Volker Lehmann

Hermann Wendt

Hans Reisinger

Holger Hubner

Michael Bianco

Siegmar Koppe

Ulrike Gruening

Martin Franosch

Wolfgang Bergner

Martin Kerber

Dietrich Widmann

Bernd Goebel

Wolfgang Hoenlein

Herbert Schaefer

Gerrit Lange

Holger Huebner

Wolfgang H&ouml;nlein

Siegmar Koeppe

Andreas Vom Felde

Gustav Beckmann

Karl Ehinger

A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

Structure and method for forming a body contact for vertical transistor cells

A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor

An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with the contact adjoining the capacitor. The first substrate and the second substrate can be connected essentially in an unadjusted manner, if capacitor elements are distributed over the first substrate and a contact surface of the contact is so large that when the substrates are connected, the contact in each case adjoins at least one of the capacitor elements, which then defines the capacitor. The capacitor may include a plurality of capacitor elements, which makes its capacitance especially high. A method is also provided for producing the integrated circuit configuration.

Integrated circuit configuration having at least one capacitor and method for producing the same

A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate. The word lines for connection of the gate electrodes of the MOS transistors run transversely with respect to the longitudinal direction of the source/drain webs.

Read-only memory cell device and method for its production

An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D,) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W,) adjoin at both sidewalls. For folded bit lines (B,), respectively two word lines (W,) can be formed in the trenches (G,). The elements of semiconductor structures neighboring along one of the trenches (G,) are then arranged in alternation at a sidewall of the trench (G,) and at a sidewall of a neighboring trench (D,). A storage capacitor can be arranged over a substrate (,) or can be buried in the substrate (,). The connection of the selection transistor to a bit line (B,) can ensue in many ways.

DRAM cell arrangement and method for the manufacture thereof

A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.

Read-only memory cell configuration with trench MOS transistor and

For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Method for manufacturing a capacitor for a semiconductor arrangement

Semiconductor testing apparatus

Semiconductor component for vertical integration and manufacturing method

A method of manufacturing a semiconductor component, wherein capacitances occurring between contacts, interconnects or metallizations are reduced by filling cavities with air or gas is provided. The cavities are produced between the semiconductor material and a passivation layer in a region wherein the interconnects are surrounded by dielectric and are subsequently closed by a further passivation layer.

Method of manufacturing semiconductor components

A component having a movable micro mechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Micromechanical semiconductor components and manufacturing method

Process for producing semiconductor components between which contact is

A component having a movable micromechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Micromechanical semiconductor component and manufacturing method therefor

Method for the production of a three-dimensional circuit arrangement

In a lateral bipolar transistor and a method for producing the same, an emitter layer and a collector layer are disposed on a structured dielectric layer. The structured dielectric layer is located in a plane of a base layer and is interrupted by the base layer in such a way that between the base layer and portions of the structured dielectric layer, the base layer is contacted on one side by the emitter layer and on the opposite side by the collector layer.

Process for producing lateral bipolar transistor

Growing community of inventors

Munich, Germany

Helmut Klose