Infineon Technologies Ag

Infineon Technologies Austria Ag

Helmut Brech

Albert Birner

Matthias Zigldrum

John Twynam

Michaela Braun

Jan Ropohl

Carsten Ahrens

Rudolf Berger

Christian Eckl

Olaf Storbeck

Simone Lavanga

Haifeng Sun

Thorsten Meyer

Roland Rupp

Guenther Ruhl

Martin Gruber

Wolfgang Lehnert

Thorsten Scharf

Richard Wilson

Oliver Häberlen

A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.

Method of fabricating a semiconductor device

A Group III nitride-based transistor device is provided that has a gate drain capacitance (C), a drain source capacitance (C) and a drain source on resistance (RDSon). A ratio of the gate drain capacitance (C) at a drain source voltage (V) of 0V, C(0V), and the gate drain capacitance Cat a value of V>0V, CV, is at least 3:1, wherein Vis less than 15V.

Group III nitride-based transistor device

A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

Selective laser annealing method

In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness t, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.

Semiconductor device and method for fabricating a semiconductor wafer

In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

Group III nitride device and method of fabricating a Group III nitride-based device

In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

Group III nitride-based transistor device having a field plate

A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

Semiconductor device and method of fabricating a semiconductor device

A semiconductor device includes a composite layer having a first and second opposing surfaces. The composite layer includes a mesa and a first insulating layer. The mesa has top and bottom surfaces and side faces. The side faces are embedded in the first insulating layer. The mesa includes a Group III nitride-based multilayer structure providing a Group III nitride based device having first and second electrodes arranged on the mesa top surface. First and second outer contacts are positioned on the second surface of the composite layer. A first conductive via extends through the first insulating layer and is electrically coupled to the first electrode on the mesa top surface and to the first outer contact. A second conductive via extends through the first insulating layer and is electrically coupled to the second electrode on the mesa top surface and to the second outer contact.

Semiconductor device and method

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

Selective thermal annealing method

In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

Through vias and methods of formation thereof

A packaged amplifier circuit includes an RF package with a die pad, and RF input and output leads extending away from the die pad opposite directions. An RF transistor die is mounted on the die pad such that a first outer edge side of the RF transistor die faces the first RF lead and a second outer edge side of the RF transistor die faces the second RF lead. A passive electrical connector is integrally formed in the RF transistor die. The passive electrical connector includes a first end connection point closer to the first outer edge side, and a second end connection point closer to the second outer edge side. A first discrete reactive device is mounted on the die pad between the first outer edge side and the first RF lead. The passive electrical connector electrically couples the first discrete reactive device to the second RF lead.

RF amplifier with impedance matching components monolithically integrated in transistor die

A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

LDMOS transistor and method

In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a lateral transistor arranged in the front surface of the semiconductor substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines side walls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source of the lateral transistor.

LDMOS transistor

In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.

Growing community of inventors

Lappersdorf, Germany

Helmut Brech