International Business Machines Corporation

Hellmuth R Geng

Arnold Blum

Johann Hajdu

Udo Wille

Guenter Knauft

Fritz Irro

Dieter Bazlen

Dietrich W Bock

Herbert Chilinski

Hermann Schulze-Schoelling

Siegfried Neuber

Rolf Berger

Bernd Spaeth

In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

Clock check circuits using delayed signals

In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

Arrangement for micro instruction control

A parallel adder with sequential carry ripple is subdivided into sections. Detector circuits are distributed over the various digit positions of the adder. Each detector circuit receives the digit pairs of the input operands of at least one adder position. The detection circuits indicate the beginning or the end of a carry ripple chain by testing the condition 'both input digits zero or both input digits one'. Via a coder, the output signals of the detection circuits are combined in the form of group indicating signals, each of which corresponds to a predetermined distance between the digit positions. By means of the group indicating signals a clock circuit is controlled in such a manner that the operating time is limited to the time required for carry rippling.

Binary parallel computing arrangement for additions or subtractions

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Herrenberg, Germany

Hellmuth R Geng