Intel Corporation

Duke University

Helia A Naeimi

Shih-Lien L Lu

Shigeki Tomishima

Charles Augustine

Arvind Srinivasan

Wei Wu

Ralph Nathan

James W Tschanz

David Pardo Keppel

Robert G Southworth

Daniel J Sorin

Georgios Panagopoulos

Qi Zeng

Qing Ma

Hung Phi Nguyen

Gautham N Chinya

Daniel Daly

Jawad Nasrullah

John L Gustafson

James Earl McCormick, Jr

Ramakrishna Huggahalli

Jonathan A Dama

Roberto Penaranda Cebrian

Karl S Papadantonakis

Karthik Sankaranarayanan

Stephen J Tarsa

Namrata Limaye

Sivakumar Munnangi

Jim McCormick

Gargi Saha

Examples described herein relate to a Transport Layer Security (TLS) offload engine to: based on detection of encrypted data unassociated with a previously detected data header: search for one or more data headers; identify at least two candidate data headers for validation; and based on receipt of an indication that the at least two candidate data headers are valid, perform decryption of received data in one or more packets. In some examples, the TLS offload engine is to: based on receipt of an indication that one or more of the at least two candidate data headers is not a valid header, search for two or more other candidate data headers.

Offload of decryption operations

Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

Shared memory mesh for switching

Examples herein relate to allocation of an intermediate queue to a flow or traffic class (or other allocation) of packets prior to transmission to a network. Various types of intermediate queues are available for selection. An intermediate queue can be shallow and have an associated throughput that attempts to meet or exceed latency guarantees for a packet flow or traffic class. Another intermediate queue is larger in size and expandable and can be used for packets that are sensitive to egress port incast such as latency sensitive packets. Yet another intermediate queue is expandable but provides no guarantee on maximum end-to-end latency and can be used for packets where dropping is to be avoided. Intermediate queues can be deallocated after a flow or traffic class ends and related memory space can be used for another intermediate queue.

On-demand packet queuing in a network device

Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Prefetcher for delinquent irregular loads

Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

Adaptive error correction in memory devices

Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

Apparatus, system, integrated circuit die, and method to determine when to bypass a second level cache when evicting modified data from a first level cache

Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.

Apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line from a second memory device

Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. The increased current level may cause a reset of all bits in the location.

Destructive reads from spin transfer torque memory under read-write conditions

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Magnetic storage cell memory with back hop-prevention

A data processing device is configured to deploy, in response to an intermittent source of power, opportunistic power management strategies to manage harvested energy based on an expected amount of energy available to the data processing device and on expected energy expenditures defined by data processing and memory content control writing performed by the data processing device.

Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory

Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.

Write operations in spin transfer torque memory

Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as spin transfer torque (STT) memory is to be followed by a write operation to the location. Additionally, a current level associated with the read operation may be increased, wherein the read operation is conducted from the location at the increased current level. In one example, the increased current level causes a reset of all bits in the location.

Embodiments include apparatuses and systems including a circuit which increases a speed of removal of data stored in a memory cell. In embodiments, the circuit includes a first discharge device coupled to an access transistor of a memory cell and coupled to an output terminal of a charge pump circuit to pull up a first voltage level at the output terminal to ground in response to a signal to accelerate leakage of a first leakage current; and a second discharge device coupled to a voltage generator circuit to pull down a second voltage level at a cell plate node of the memory cell to ground in response to the signal to accelerate leakage of a second leakage current, wherein the cell plate node is coupled to a storage node of the memory cell by a capacitor. Other embodiments may also be described and claimed.

Apparatuses, methods, and systems for increasing a speed of removal of data from a memory cell

In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

Magnetic field-assisted memory operation

A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU. The second register is separate from the first register.

Growing community of inventors

Santa Clara, CA, United States of America

Helia A Naeimi