International Business Machines Corporation

Infineon Technologies Ag

Samsung Electronics Co., Ltd.

Globalfoundries Singapore Pte. Ltd.

Helen Wang

Scott David Halle

Allen H Gabor

Haoren Zhuang

Christopher V Baiocco

Carl John Radens

Matthew Earl Colburn

Daniel J Jaeger

Len Yuan Tsou

Andrew Lu

Patricia Argandona

Faisal Azam

Effendi Leobandung

Oleg Gluschenkov

Vijay Narayanan

Kevin K Chan

Terence B Hook

Fei Liu

Richard Stephan Wise

Min Yang

Dae-Gyu Park

Xinhui Wang

Howard Smith Landis

Kenneth Jay Stein

Masaharu Kobayashi

Henning Haffner

Alois Gutmann

Scott Marshall Mansfield

Xiang Hu

Jingyu Lian

Young-Hee Kim

Habib Hichri

Matthias Lipinski

Martin Burkhardt

Melanie J Sherony

Klaus Herold

Zachary Baum

Chong Kwang Chang

Jay M Shah

Jason E Meiring

Arifuzzaman (Arif) Sheikh

Chendong Zhu

Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Process variability tolerant hard mask for replacement metal gate finFET devices

A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

Metal oxide semiconductor field effect transistor (MOSFET) gate termination

Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.

Semiconductor device manufacturing methods

A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.

Integrated circuit system with reduced polysilicon residue and method of manufacture thereof

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Self-limiting oxygen seal for high-K dielectric and design structure

A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer

An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.

Methods for forming a composite pattern including printed resolution assist features

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Integrated circuits and methods of design and manufacture thereof

Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.

Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.

Systems and methods for overlay shift determination

The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.

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Lagrangeville, NY, United States of America

Helen Wang