Infineon Technologies Ag

National Semiconductor Corporation

Silicon Line Gmbh

National Semiconductor Germany Ag

Heinz Werker

Robert Callaghan Taft

David Brian Barkin

Pier Francese

Christian Ebner

Dirk Killat

Ordwin Haase

Siegfried Hart

In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed&#x2014;that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and&#x2014;that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived.

Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators

In order to provide a circuit arrangement () and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate,

Circuit arrangement and method for clock and/or data recovery

A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Continuous synchronization for multiple ADCs

The invention relates to a phase locked loop or 'PLL' () and a method for the operation of a PLL (), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKinor CKin) and a second clock signal (CKinor CKin) for use as the input clock signal of the PLL (). According to the invention, for the clock signal (CKinor CKin) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKinor CKin) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used. The PLL output signal (CKout) can thus follow more quickly any switch-over-related frequency change of the clock signal being used.

Switchable phase locked loop and method for the operation of a switchable phase locked loop

The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (), but is subjected beforehand to a digitally adjustable phase displacement (). There originates an 'auxiliary sampling clock signal' (CK&#x3c;&#x3e;). The sampling () delivers a first, more significant digital component (OUT&#x3e;) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT&#x3e;) a phase displacement () is undertaken and a second digital component (OUT&#x3e;) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK&#x3c;&#x3e;) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).

Digital phase detector and a method for the generation of a digital phase detection signal

A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection circuit connected to a digital phase detector and an analog phase detector for avoiding a phase quantization error. The lock detection circuit activates the analog phase detector to run simultaneously with a digital phase detector if the phase error is zero. The activated analog phase detector regulates the output clock signal of the digitally controllable oscillator in a continuously variable manner until the respective clock signal edges of the output clock signal and the reference clock signal are fully synchronous. The lock detection circuit deactivates the analog phase detector and continuously checks and regulates the digital phase detector until the phase error between the output clock signal and the reference clock signal is zero.

Low jitter analog-digital locker loop with lock detection circuit

The output driver circuit of an integrated circuit has several pairs of driver circuits and driver control circuits as well as a control device. Each pair of driver control circuit and driver circuit forms a driver stage. The driver stages are connected in series. Based on the input signal of the output driver circuit, the control device switches the signal direction through the succession of driver stages in such a way that, at the time the output driver circuit is switched either on or off, the driver stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.

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Huglfing, Germany

Heinz Werker