International Business Machines Corporation

Essilor International (compagnie Generale D'optique)

Elpis Technologies Inc.

Essilor International

Heinz Schmid

Heike E Riel

Emmanuel Delamarche

Bruno Michel

Kirsten Emilie Moselund

Mikael T Bjoerk

Mattias B Borg

Walter Heinrich Riess

Alexander Bietsch

Joachim Knoch

Heiko Wolf

Siegfried Friedrich Karg

Hans Biebuyck

Hans-Werner Fink

David Juncker

Bernd W Gotsmann

Lukas Czornomaz

Michel Bruno

Veeresh Vidyadhar Deshpande

Oliver Hayden

Vladimir Djara

Stephan Wirths

Benedikt F Mayer

Fabrizio Nichele

Roger Morin

Markus Fabian Ritter

Philipp Staudinger

Werner Stocker

Guy M Cohen

Sarunya Bangsaruntip

Jean-Paul Cano

Emanuel Loertscher

Gerhard Keller

Urs Kloter

Cédric Begon

Johannes Gooth

Utz Herwig Hahn

Bogdan Cezar Zota

Yannick Baumgartner

Andre Bernard

Bettina Stocker

Alan Molinari

Lorenzo Rocchino

Matthias Geisler

Described is an integrated circuit device comprising one or more interconnects. Each interconnect of the one or more interconnects can be structured as a stack of layers including distinct topological layers, where each of the distinct topological layers can be a layer of topological material. Any two successive layers of the distinct topological layers can be separated by one or more interfaces, each forming a boundary between two consecutive layers of the stack, where the two consecutive layers can be engineered to preserve topologically protected surface states of each of the any two successive layers of the distinct topological layers.

Integrated circuit device with interconnects made of layered topological materials

Techniques that can facilitate high-transparency semiconductor-metal interfaces are provided. In one example, a method can comprise forming a silicon on insulator (SOI) over a wafer. The method can further comprise depositing a metal on the SOI. The method can further comprise forming a structure by dry-etching the metal and dry-etching the SOI. The method can further comprise forming a template over the structure. The method can further comprise etching a portion of the SOI for removal under the metal. The method can further comprise growing a semiconductor where the portion of SOI was removed.

High-transparency semiconductor-metal interfaces

Embodiments of the invention relate to a method for fabricating a semiconductor structure comprising a semiconductor material, and a semiconductor substrate fabricated from the method. The method can include a step of providing a template structure. The template structure can comprise an opening, a cavity and a seed structure. The seed structure can comprise a seed material and a seed surface. An inner surface of the template structure can comprise at least one metallic surface area comprising a metallic material. The embodied method further comprises a step of growing the semiconductor structure within the cavity of the template structure from the seed surface along the metallic surface area.

Fabrication of a semiconductor device

A method for fabricating a metastable crystalline structure is provided. The method includes providing a base substrate, wherein the base substrate comprises an insulating layer. The method further includes providing a metastable seed crystal on the base substrate, wherein the metastable seed crystal has a predefined metastable crystal phase or a predefined metastable composition. The method further includes forming a template structure above the base substrate, wherein the template structure covers at least a part of the metastable seed crystal. The method further includes growing the metastable crystalline structure with the predefined metastable crystal phase or the predefined metastable composition of the seed crystal inside the template structure. The growing of the metastable crystalline structure is nucleated from the seed crystal. Crystalline structures produced by the methods described herein are also provided.

Method for growing a metastable crystalline structure which is a 2-dimensional planar film from a nanowire metastable seed crystal provided inside a template structure

A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.

Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Plasmonic quantum well laser

A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

Fabrication of semiconductor substrates

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2&#xd7;10nm. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Semiconductor nanowire fabrication

An electrical junction comprising a first pair of leads and a second pair of leads. The first pair of leads and the second pair of leads comprise a Weyl semimetal. The junction comprises an electrical crossing arranged between the leads of the first pair and the leads of the second pair and is configured to provide an electrical connection between the leads of the first pair and the leads of the second pair. A related electrical device and a related neural network may be also presented.

Electrical junction for facilitating an integration of electrical crossing

Electrical junction

Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

Fabrication of semiconductor junctions

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Array of optoelectronic structures and fabrication thereof

A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

A braiding element and a method for operating the braiding device, a structure of braiding devices as well as an array of braiding devices for controlling parafermions for quantum computing may be provided. The braiding device comprises a first wire layer and a second wire layer, a superconductor layer arranged in vertical sandwich-style between the first and the second wire layer such that a device structure is built and a plurality cascades of gate electrodes such that one of the plurality of cascades of gate electrodes is arranged at the first quantum wire layer and at the second quantum wire layer of each of the three legs.

Parafermion braiding device

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Waedenswil, Switzerland

Heinz Schmid