Siemens Aktiengesellschaft

Siced Electronics Development Gmbh & Co Kg

Norstel Ab

Infineon Technologies Ag

Infineon Technologies Austria Ag

Heinz Mitlehner

Dietrich Stephani

Peter Friedrichs

Reinhard Maier

Benno Weis

Manfred Bruckmann

Eric Baudelot

Hans-Joachim Schulze

Reinhold Schörner

Wolfgang Bartsch

Rudolf Elpelt

Reinhold Kuhnert

Alexandre Ellison

Ulrich Weinert

Björn Magnusson

Asko Vehanen

Frank Dieter Pfirsch

Jenoe Tihanyi

Gerd Griepentrog

Michael Stoisiek

Peter Kaluza

Christian Schreckinger

Hermann Zierhut, Deceased

Gerhard Schr&ouml;ther

Gerald Deboy

Roland Rupp

Michael Treu

Hermann Zierhut

Larissa Wehrhahn-Kilian

Ernst W Haas

Reinhold Sch&ouml;rner

Tibor Salanki

Jenö Tihanyi

Joachim Martin

Erich Zerbian

Bernd Kolbesen

Karl-Otto Dohnke

Ingeborg Zierhut

Karl Dohnke

A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 10cmand a carrier lifetime of at least 50 ns.

Lightly doped silicon carbide wafer and use thereof in high power devices

A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5&#xd7;10cm, and a concentration of transition metals impurities less than 5&#xd7;10cm. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700&#xb0; C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.

A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.

Method for making an integrated circuit including vertical junction field effect transistors

The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (), a current path that runs within the first semiconductor region () and a channel region (). The channel region () forms part of the first semiconductor region () and comprises a base doping. The current (I) in the channel region () can be influenced by means of at least one depletion zone (). The channel region () contains an n-conductive channel region () for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region () is produced by ionic implantation in an epitaxial layer () that surrounds the channel region ().

Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure

A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 10cmand a carrier lifetime of at least 50 ns at room temperature.

A switching device includes a working circuit, to which an operating voltage can be or is applied to which has at least one electronic switching element. This switching element includes at least one control terminal for applying a switching signal and is switched off or switched on depending on the switching signal. At least one electronic protection element is for protecting the switching element in its switched state from excessive Joule losses in the event of danger, especially in the event of an overload or a short circuit. The protection element bears the predominant part of the operating voltage that is released at the working circuit. The switching device includes a switching-off device, which, in the event of danger, automatically switches the switching element to the switched off state, using the energy contained in the operating current or the operating voltage passing through the working circuit or the voltage that is released at the working circuit or at the protection element exceeds a predetermined upper limit value.

Electronic switching device

A switching device includes at least one MOSFET switching element and at least one JFET protective element, which is connected electrically in series to the switching element and which limits the electric current to a maximum current (saturated current) and control elements, which increase the maximum current of the JFET protective element during the closing operation or in a time-delayed manner, at least in the temporal mean, to at least a higher value and subsequently reduce said maximum current to at least a lower value. The advantage of said switching device is that it allows higher starting or closing overcurrents, which are subsequently limited.

Electronic switching device and an operating method thereof

A semi-conductor structure for controlling and switching a current has a switch element and an edge element. The switch element contains a first semi-conductor area of a first conductivity type contacted by way of an anode electrode and a cathode electrode, a depletion area that is arranged inside the first semi-conductor area and that can be influenced by a control voltage applied to the control electrode for the purpose of current control, and an island area of a second conductivity type that is buried inside the first semi-conductor area. The edge element contains an edge area of the second conductivity type that is buried inside the first semi-conductive area and that is formed on a common level with the buried island area, in addition to an edge terminating area of a second conductivity type adjacent the edge area.

Semiconductor structure with a switch element and an edge element

A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least one zone of a second conductivity type, opposite to the first conductivity type, is embedded. Regions of the second conductivity type are provided in the semiconductor body in a plane running substantially parallel to the surface of the surface region. The regions are in this case sufficiently highly doped that they cannot be depleted of charge carriers when a voltage is applied.

Vertical semiconductor component having a reduced electrical surface field

A switching device for switching at a high operating voltage includes an LV switching element and a first HV switching element that are connected together in a cascode circuit. Furthermore, at least a second HV switching element is connected in series with the first HV switching element. A first protection element is connected between the HV grid terminals of the first and second HV switching elements, respectively.

Switching device for switching at a high operating voltage

A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Junction field-effect transistor with more highly doped connecting region

A semiconductor configuration for current control has an n-type first semiconductor region with a first surface, a p-type covered island region, within the first semiconductor region, with a second surface, an n-type contact region arranged on the second surface within the island region and a lateral channel region, formed between the first and second surface as part of the first semiconductor region. The channel is part of a current path from or to the contact region. The current within the lateral channel region may be influenced by at least one depletion zone. A lateral edge of the lateral channel region extends as far as the contact region.

Semiconductor construction with buried island region and contact region

A protection device includes a measurement device and a downstream evaluation device. The evaluation device is a unit for early short-circuit identification which actuates a semiconductor switch, which is preferably produced based on silicon carbide. The unit for early short-circuit identification preferably operates with switching thresholds which can be predetermined for the product of the current and the current rate of change, or on the basis of tolerant locus curves. In the latter case, different power factors (0.1<cos <0.9) are used in the locus curves in a locus curve representation of the current and current rate of change. The semiconductor switch preferably contains two back-to-back series-connected switching elements based on silicon carbide.

Protection device for low voltage networks

J-FET having a first semiconductor region ( ), which comprises a first contact ( ) with a highly doped contact layer ( ) serving as a source disposed between two second contacts ( ) serving as a gate on its first surface ( ). The three contacts ( ) are each connected to a respective second semiconductor region ( ). The first and second semiconductor regions ( ) are of opposite conductivity types. The second semiconductor regions ( ) connected to the second contacts ( ) extend in the first semiconductor region ( ) below the second semiconductor region ( ) that is connected to the first contact ( ), with the result that the three second semiconductor regions ( ) at least partially overlap in a projection onto a horizontal plane and a channel region ( ) is formed between the three second semiconductor regions ( ) in the first semiconductor region ( ).

J-FET semiconductor configuration

A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Growing community of inventors

Uttenreuth, Germany

Heinz Mitlehner