Infineon Technologies Ag

Siemens Aktiengesellschaft

Heinz Mattes

Sebastian Sattler

Peter Gregorius

Paul Georg Lindt

Ralf Arnold

Stephane Kirmser

Michael Goessel

Herbert Eichfeld

Andreas Leininger

Thomas Piorek

Klaus Standner

Claus Dworski

Hermann Obermeir

Olaf Stroeble

A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler's number as the base, and in a further phase has a profile of a falling exponential function with Euler's number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.

Apparatus and method for the characterization of analog-to-digital converters

A signal generating circuit, may include an analog signal generator having an output and a control input, the analog signal generator configured to generate at the output an analog output signal in accordance with a timing parameter; an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the analog signal generator, the ADC configured to generate a sequence of signal values dependent on the analog signal received at the input; a configurable digital signal generator comprising an output and a control input, the digital signal generator configured to generate a digital output signal in accordance with signal parameters received at the control input; and a control circuit having an input coupled to the output of the ADC.

Signal generating circuit

An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream T. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.

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M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tlong. The test signal is sampled with N sampled values at a sampling frequency f=1/T. Also, N*T=M*T, where N&#x3e;M. The sampled values are numbered progressively by n, for which 0&#x2266;n &#x2266;N&#x2212;1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tis calculated by K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's iperiod or the last sampled value before a test signal zero crossing during the reference signal's iperiod. Either only rising or only falling zero crossings are taken into account.

Measuring device and method for measuring relative phase shifts of digital signals

A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.

Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device

An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

Electrical circuit for measuring times and method for measuring times

To estimate physical properties of a wired or wireless transmission channel it is proposed to sample a signal, received via the transmission channel, for example a system response of the corresponding transmission system, in order, on the basis of the sampled values thus obtained, to ascertain the moments of the order 0 . . . n of the received signal. Using these moments of the order 0 . . . n, n parameters of a transmission function of the transmission channel can be determined, wherein the parameters can be polynomial coefficients, zero points or coefficients of a residual notation of the transmission function. Using this transmission function the physical properties of the transmission channel, such as the attenuation and dispersion properties, can be determined exactly or at least approximately assessed.

Method and device for estimating channel properties of a transmission channel

A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency fat its output. A phase modulator generates a test clock subjected to jitter and having the clock frequency fat its output. The output of the data pattern generator is connected to a terminal for connection to a data input of a semiconductor component to be tested. The output of the phase modulator is connected to a terminal for connection to a clock input of a semiconductor component to be tested. An evaluation device determines the jitter parameters of the input signal at the input of the data device from the low-frequency component of the input signal. In this case, the low-frequency component contains only frequency components of frequencies which are less than half the sampling frequency f/2.

Device and method for measuring jitter

The electronic test circuit for an integrated circuit to be tested has an input for receiving an analog data stream (), a programmable digital line emulator (TPE) for emulating properties of a transmission path and an output for emitting an analog data stream () having a signal-to-noise ratio which can be adjusted using the programmable digital line emulator (TPE).

Electronic test circuit for an integrated circuit and methods for testing the driver strength and for testing the input sensitivity of a receiver of the integrated circuit

A test device and method is disclosed. In one embodiment, the test device includes a precision signal generator for generating a test signal, which generator is connected via a respective connecting line to a respective input contact intended for connection to an input of an integrated circuit, and at least one reference signal generator for generating a reference signal. Furthermore, at least one comparator unit is provided for a respective input contact said comparator unit being able to be operated in a test mode. In the test mode, the test signal is compared with the reference signal. The precision signal generator is turned off by the comparator unit if the test signal exceeds or falls below the reference signal.

Device and method for testing integrated circuits

A method for testing AD converters () may have the steps of a) producing a digital test signal, b) producing an analog test signal as input signal for the AD converter () from the digital test signal, c) producing a sinusoidal, digital reference signal whose frequency is equal to or an integer multiple of the frequency of the analog test signal, d) mixing the test response from the AD converter () with the sine and the cosine of the digital reference signal to form mixed signals, e) determining the DC components of the mixed signals, and f) determining at least one of the parameters including amplitude, power components and phase angle for a fundamental or harmonic of the test response from the DC components of the mixed signals.

Test apparatus and method for testing analog/digital converters

A test apparatus includes a signal source that generates a radio-frequency test signal and is connected to the input connection of an arrangement. The arrangement simultaneously supplies an electrical radio-frequency signal to a plurality of receivers and via a plurality of distribution lines. Each distribution line includes an end with an output connection that applies the power-matched test signal to a respective external component.

Test apparatus with low-reflection signal distribution

A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

Method and filter arrangement for digital recursive filtering in the time domain

An electrical circuit including a test circuit and a method of testing electrical circuits is disclosed. In one embodiment, the circuit includes a electrical short-circuit protective circuit according to the invention for protecting an input contact against short-circuit having an input which is intended for connection to a signal generator, and an output which is intended for connection to a input contact. The input contact can be decoupled from the region lying upstream of the input of the electrical short-circuit protective circuit by the electrical short-circuit protective circuit.

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Munich, Germany

Heinz Mattes