Motorola Corporation

Marvell International Limited

Freescale Semiconductor,inc.

Heinz Bernhard Maeder

Anil Gercekci

Patrick Clement

Cao-Thong Tu

Gene A Schriber

King Chu Tsai

To calibrate a bandpass filter, a received signal strength corresponding to a received communication channel is determined. A variable element of the bandpass filter is adjusted based on the received signal strength of the received communication channel to calibrate the bandpass filter.

Method and apparatus for calibrating a bandpass filter

A hybrid sigma-delta converter that includes a continuous-time circuit that processes an input signal and generates a first output signal, an interface circuit that receives the first output signal from the continuous-time circuit and filters the first output signal thereby generating a second output signal, and a discrete-time circuit that processes the second output signal received from the interface circuit. The interface circuit further reduces the coupling of noise generated from the operation of the discrete time circuit to the preceding continuous-time circuit.

Interface for hybrid sigma-delta data converter

Amplitude level control circuit for an oscillator comprising first means arranged to generate a first current for driving the oscillator; and second means arranged to generate a second current such that in direct current conditions the second current is arranged to be a predetermined ratio of the first current, wherein the second current is arranged to be added to a reference current to form a feedback current such that in direct current conditions the first current is determined by the reference current, the ratio of the feedback current and first current and the ratio of the first current and second current, wherein the second means is further arranged to reduce the second current as oscillations of the oscillator increase, thereby reducing the first current.

Amplitude level control circuit

This invention relates to a video analog-to-digital converter (ADC) and to a method of digitizing a video analog signal. The video ADC (2) comprises a clock for providing a clock signal (HZ) which clocks a horizontal line rate, dither generating means (10) for generating a dither pattern synchronized with the horizontal clock signal. A preferred dither pattern comprises a staircase sequence of voltage steps, the voltage level of each step being constant for at least one horizontal line. The video ADC further comprises combining means for combining the dither pattern with the analog video signal, digitizing means (4, 6) for converting the combined dither pattern and video signal to a sequence of digital values and correcting means (12) coupled to the digitizing means and the dither generating means for subtracting the dither pattern from the digitized sequence of values so as to generate a sequence of digital values which represent said analog video signal. By superimposing a dither pattern to the analog video signal at the horizontal line rate, the operating point of the ADC can be altered. As a result, step errors of the ADC do not occur at the same horizontal position on a line and are therefore less visible. In a preferred arrangement, the dither pattern is superimposed on a plurality of reference voltage levels generated by bias means (8) and which are applied to the digitizing means so that the dither pattern and the analog video signal are combined in the digitizing means.

Video analog-to-digital converter

An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

Means and method for disabling access to a memory

A method of automatically searching for an RF carrier uses a synthesized frequency. The synthesized frequency is generated by a voltage controlled oscillator which is part of a phase locked loop. The phase locked loop has a programmable divider which is controlled by a phase locked loop controller. The phase locked loop controller receives inputs from a frequency discriminator which is a portion of an RF receiver which is receiving the RF signals. The search is accomplished by using a frequency sweep rather than searching for a carrier at allocated frequency positions. When the search is initiated, large frequency steps are taken until a carrier signal is passed up and then the steps are decreased in size and inversed until the carrier signal is encountered again.

Method for automatically searching for an RF station

A MOS latch circuit is provided which has a fast response and is sensitive to low level input clock signals. The latch circuit has two load devices which are connected to a pair of cross-coupled transistors. A controllable current source is used to control the current flow through the cross-coupled pair of transistors. A first coupling transistor is connected between the input of the cross-coupled pair of transistors and a second controllable current source. A second coupling transistor is connected between a second input of the cross-coupled pair of transistors and to the second controllable current source. The first and second coupling transistors are enabled by input data signals to the latch circuit while the first and second controllable current sources are controlled by clock signals.

MOS Latch circuit

An oscillator for generating oscillation signals. The oscillation signals are initiated in response to an applied start signal and begin at a fixed predetermined phase. Hence, the oscillator is suitable for use in phase dependent timing systems to inhibit phase jitter which could otherwise occur. The oscillator includes an inverting amplifier and phase shifting feedback network for establishing and maintaining oscillations. The phase shifting feedback network includes a series coupled coil between the output and input of the inverting amplifier. A bias circuit is included for injecting direct current through the coil when oscillation is inhibited to generate a direct current magnetic field in the coil. The magnetic field ensures that, in response to the start signal, the oscillation signals begin at said fixed phase.

Start stop oscillator having fixed starting phase

An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET. The drain of the input MOSFET is connected to the output of the input buffer circuit. The source of the input MOSFET is connected to the drain of a second depletion mode MOSFET having its source connected to ground and its gate connected to a V.sub.DD voltage conductor. A load circuit is coupled between the V.sub.DD voltage conductor and the output, and consists of an enhancement mode MOSFET and a depletion load MOSFET coupled in series between output and V.sub.DD voltage conductor. A third depletion mode MOSFET has its drain connected to the V.sub.DD voltage conductor, its source connected to the source of the input MOSFET, and its gate connected to the output. The positive gain (or negative slope) portion of the switching characteristic of the input buffer circuit extends substantially all the way between the high and low output levels.

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Weinfelden, Switzerland

Heinz Bernhard Maeder