Nxp B.v.

Heimo Scheucher

Tonny Kamphuis

Stefan Lemsitzer

Guido Albermann

Ewald Bergler

Michael Ziesmann

Claus Dieter Grzyb

Florian Schmitt

David Ceccarelli

Hans Cobussen

Guido Dormans

Laurentius De Kok

Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.

Maximizing potential good die per wafer, PGDW

A semiconductor wafer () having a regular pattern of predetermined separation lanes () is provided, wherein the predetermined separation lanes () are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Semiconductor wafer and method of producing the same

Integrated circuits () on a wafer comprise a wafer substrate () and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit () and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (), process control modules () as integral parts. The process control modules () are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Integrated circuits on a wafer and methods for manufacturing integrated circuits

A chip () has a substrate (), an integrated circuit () provided on the substrate (), a plurality of conductor zones (ME, ME, ME, ME, ME) and a passivating layer () provided to protect the conductor zones and the integrated circuit, through-holes () being provided in the passivating layer () through which chip contacts () are accessible, wherein additional chip contacts () and connecting conductors () are provided on the passivating layer () and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.

Chip having two groups of chip contacts

Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.

Individual ROM codes on a single reticle for a plurality of devices

Integrated circuits () on a wafer comprise a wafer substrate () and a structure applied on a surface () of the wafer substrate (). The structure forms a plurality of integrated circuits () formed on the wafer substrate () and the integrated circuits () are separated by saw lines (). The structure comprises a plurality of superposed layers (-) formed on the wafer substrate () and a top layer () formed on the superposed layers (-). The integrated circuit () on the wafer further comprise a plurality of alignment marks () intended for aligning a separating device () for separating the integrated circuits () on the wafer into individual integrated circuits () during a separation process, wherein the alignment marks () are formed from at least one of the superposed layers (-).

Integrated circuits on a wafer and method for separating integrated circuits on a wafer

Integrated circuits () on a wafer comprise a wafer substrate (), a plurality of integrated circuits () formed lattice-like in rows and columns on the wafer substrate (), and first and second saw lines () separating the integrated circuits (). The first saw lines () run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines () run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits () on the wafer further comprise a plurality of process control modules () formed on the wafer substrate () such that a given process control module () of the plurality of process modules () is bounded by two consecutive first saw lines () as well as by two consecutive second saw lines ().

Integrated circuits (Ia, Ib) on a wafer () comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (). Only the first integrated circuits (Ia) comprise each at least one bump () not contacting their relevant electric circuits ().

Integrated circuits on a wafer and method of producing integrated circuits

A data carrier () comprises a data circuit () arranged on a substrate () and data transmission unit () being connected to the data circuit (). The data carrier () further comprises at least one strain gauge unit () being adapted to measure strains exerted on the substrate () and to transmit a deactivating signal (DE) to the data circuit () if the measured strains exceed a defined deactivating strain threshold. If the data circuit () receives the deactivating signal (DE), the data circuit () interrupts a data exchange with an external data reader/writer () via the data transmission unit ().

Data carrier comprising strain gauge means

In a wafer () with a number of exposure fields (), each of which exposure fields () comprises a number of lattice fields () with an IC () located therein, two groups () of dicing paths () are provided and two control module fields (A, A, B, B, C, D, D, E, E, F) are assigned to each exposure field (), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A, OCM-A, OCM-BI, OCM-B, OCM-C, OCM-D, OCM-D, OCM-E, OCME, OCM-F), wherein a first control module field (OCM-A, OCM-B, OCM-C, OCMD, OCM-E, OCM-F) of each exposure field () is located between a first edge (R, S, T, U, V, Z) and a row of lattice fields () of the exposure field () in question and a second control module field (OCM-A, OCM-B, OCM-D, OCM-E) is located between two rows of lattice fields () of the exposure field () in question, which are arranged adjacent to a second edge (R, S, U, V), and wherein both the first control module fields (OCM-A, OCM-B, OCM-C, OCM-D, OCM-E, OCM-F) and the second control module fields (OCM-A, OCM-B, OCM-D, OCM-E) each lie in a first dicing path ().

Wafer with optical control modules in dicing paths

In a wafer () with a number of exposure fields (), each of which exposure fields comprises a number of lattice fields () with an IC () located therein, two groups () of saw paths () are provided and two control module fields (A, A, B, B, C, C, D, D) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A, OCM-A, OCM-B, OCM-B, OCM-C, OCM-C, OCM-D, OCM-D) and lies within the exposure field in question and comprises a plurality of control module field sections (A, A. . . AIN and A, A. . . AN and B, B. . . BN and B, B. . . BN and CN and CN and DN and DN) and is distributed among several lattice grids (), wherein each control module field section (Ato DN) is located in a lattice field and contains at least one control module component ().

Wafer with optical control modules in IC fields

In an integrated circuit () having a substrate () and having a signal-processing circuit () which is produced at a surface () of the substrate (), there is provided on the substrate surface () a protective layer () that has at least one aperture () through which a second contact pad () is electrically and mechanically connected to a first contact pad (), wherein the second contact pad () is of a height of at least 15 &#x3bc;m and projects laterally beyond the aperture () on all sides and is seated on the protective layer () by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 &#x3bc;m and 15 &#x3bc;m, and wherein at least one element of the signal-processing circuit (), and preferably only one capacitor () of the signal-processing circuit (), is provided opposite the first contact pad ().

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Langegg, Austria

Heimo Scheucher