Infineon Technologies Ag

Heimo Hartlieb

Michael Hausmann

Christian Heiling

Axel Reithofer

Klaus Strohmayer

Jens Barrenscheen

Clemens Kain

Martin Graefling

Hannes Reinisch

A method for a responder bus node is described herein. In accordance with one embodiment, the method includes receiving a first frame over a first data channel of a serial bus, wherein the first frame comprises at least a first header field with first header data and a first payload field with first payload data. The method further includes checking whether a first address, which is based on the first header data, is equal to a predetermined address. When the first address is equal to the predetermined address, a read operation is performed using a second address, which is based on the first payload data, and, when the first address is not equal to the predetermined address, a write operation is performed using the first address and the payload data. Furthermore, a corresponding method for a commander bus node, as well as a respective responder and commander bus node are described.

Serial bus communication without read indication

A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.

System and method for transparent register data error detection and correction via a communication bus

A system includes a bus system to connect a number of components in a chain-like structure. A first control device (e.g., microcontroller or microprocessor) is configured to control the components in a first mode of the system. A second control device (e.g., microcontroller or microprocessor) is configured to control a first subset of the components in a second mode of the system.

System and method to transmit data over a bus system

A circuit arrangement is described herein. In accordance with one exemplary embodiment, the circuit arrangement includes at least one output channel configured to be operably coupled to at least one load that is to be driven by the circuit arrangement. In the at least one output channel, the circuit arrangement includes a driver circuit configured to provide a modulated output signal, a current sense circuit configured to sense a load current passing through the load, and a feedback circuit configured to receive the modulated output signal and to determine, based on the modulated output signal, at least one digital value representing an average of the load current.

Driver circuit with current feedback

A system includes multiple devices connected in a chain-like structure, each device of the multiple devices coupled to at least one bus. A device of the plurality of devices includes a circuit configured to detect activity of a differential signal of a bus coupled to the device to cause a wakeup of the device in response to the detection.

Wakeup receiver circuit, electronic system and method to wakeup a device

A device is operated in a low power mode of operation. The device receives a differential signal that includes a first polarity signal and a second polarity signal. A slope of a first direction is detected in the differential signal and a slope of a second direction is detected in the differential signal. A wakeup of the device is caused in response to the detection of the first slope of the differential signal and the second slope of the differential signal.

Wakeup receiver circuit, electronic system and method to wake up a device

In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Signal converter and method for operating a signal converter

The invention relates to an electrical or electronic system, and more specifically, to a system with a bus, and a method to transmit data, in particular error data over a bus system. According to an embodiment, a method to transmit error data over a bus system that connects a plurality of modules/components/elements of an electronic system in a chain-like structure comprises in a first phase, transmitting information regarding what kinds of errors have occurred in the system, and in a second phase, transmitting information regarding where in the system an error has occurred.

System and method to transmit data, in particular error data over a bus system

A system including a bus, and a method to transmit data over a bus system are disclosed. According to an embodiment, a method to transmit data over a bus system includes deliberately delaying the transmission of data. The deliberate delay caused by deliberately delaying the transmission of data may be chosen to predominate stochastic delay differences.

System comprising a bus, and method to transmit data over a bus system

A system and method can be used for scaling an output of a modulator of a sigma-delta analog to digital converter and systems and a method can be used for compensating temperature-dependent variations of a reference voltage in a sigma-delta analog to digital converter. In accordance with one embodiment, a system can be used for scaling an output of a modulator of a sigma-delta analog digital converter (ADC). A decimation filter has a decimation length that is adjustable by a decimation length value received as an input to the decimation filter. The decimation filter is configured to receive the output of the modulator of the sigma-delta ADC and to decimate the received output of the modulator of the sigma-delta ADC using the received decimation length value.

System and method for operating an analog to digital converter

A current regulator and a method for regulating current are described.

Regulation of a current through an inductive load

Current regulators and related method for regulating a current through a load. The current regulator may include, for example, a first circuit configured to determine an amount of current that flows through the load; and a second circuit configured to cause a voltage to be applied across the load, the voltage having a duty cycle that depends on the amount of the current flowing through the load.

Integrating current regulator and method for regulating current

A regulator and a method for regulating a current through a load. The regulator may include, for example, a first circuit portion configured to alternately apply and remove a voltage across the load in accordance with a first signal, the voltage causing a current to flow, and a second circuit portion configured to generate the first signal so as to have a duty cycle that depends upon an amount of the current and a second signal when the amount of current is below a threshold amount, and to generate the first signal so as to have a duty cycle that depends upon the amount of the current but not the second signal when the amount of current exceeds the threshold amount.

Current regulator with current threshold dependent duty cycle

An embodiment of the invention relates to a controller that includes a delta-sigma modulator to produce a one-bit, oversampled signal representing a measured characteristic of a process, and a delta-sigma modulator to produce a one-bit, oversampled signal representing a set-point value for the characteristic. A multiplexer selects a partial sum based on a difference of the oversampled signals to produce a control signal for the process. The controller that produces the control signal for the process can be a PID controller.

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Graz, Austria

Heimo Hartlieb