Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (Crolles 2) Sas

Heimanu Niebojewski

Yves Morand

Maud Vinet

Fabrice Nemouchi

Cyrille Le Royer

Shay Reboh

Claire Fenouillet-Beranger

Louis Hutin

François Andrieu

Julien Borrel

Benoit Bertrand

Sébastien Barnola

Thomas Bedecarrats

Christophe Plantier

A Qbit spin quantum device includes juxtaposed first and second semiconducting portions, the semiconducting portions being formed in a surface layer of a semiconductor-on-insulator type substrate and disposed on an insulating layer of the substrate, the substrate being fitted with a semiconducting support layer such that the insulating layer is arranged between the support layer and the surface layer, and several pairs of front control gates, each pair being formed respectively of first and second front control gates covering a region of the first and second semiconducting portions to form first and second quantum islands, respectively. An insulating region is provided between the first and second quantal islands to enable electrostatic coupling between the first and second quantum islands. The quantum device includes a back conductive electrode vertically aligned with a coupling insulating region and being formed of a region of metal-semiconductor material alloy arranged in the support layer.

Quantum device integrating a buried metal electrode

A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.

Method for manufacturing a quantum electronic circuit

Making of a transistor structure comprising in this order:

Method for germanium enrichment around the channel of a transistor

A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

Method for manufacturing a microelectronic device

A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.

Method for manufacturing a mixed substrate

The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Method of making a transistor

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

Transistor with MIS connections and fabricating process

A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Method for making an integrated circuit

A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Air-spacer MOS transistor

A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Method of making a semiconductor layer having at least two different thicknesses

A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Growing community of inventors

Grenoble, France

Heimanu Niebojewski