International Business Machines Corporation

Heiko Michel

Benedikt Geukes

Manfred Walz

Matteo Michel

Frank Haverkamp

Joerg-Stephan Vogt

Gerald Kreissig

Benedikt Guekes

The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device (), the method comprising, determining a boot mode for booting the electronic device, wherein the determined boot mode is defined as a secure boot mode; disabling the interface, thereby prohibiting access to the component through the interface, thereby defining a secure state of the electronic device; loading a first code comprising a sequence of executable instructions to be executed for booting the electronic device; loading a second code, the second code being encrypted; and decrypting the second code and executing the second code, thereby enabling the interface, and switching the electronic device from the secure state to a debugging state.

Method for secure self-booting of an electronic device

A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

Efficiency of compression of data pages

Controlling scan access to a scan chain

Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Collecting debug data in a secure chip implementation

An integrated circuit (IC) performs self-healing and reconfiguration of a portion of the IC. In response to determining that a portion of the IC should be configured, a clock to the portion of the IC to be configured is halted. That portion of the IC is then configured using a processing core that is included in the IC. The processing core is also used to perform an intended function of the IC that is different than the configuration.

Growing community of inventors

Stuttgart, Germany

Heiko Michel