International Business Machines Corporation

Heidi L Greer

Douglas Duane Coolbaugh

Robert Mark Rassel

Kunal Vaed

Anthony K Stamper

Ramachandra Divakaruni

Steven M Shank

Arne Watson Ballantine

Herbert Lei Ho

Bomy A Chen

Rajarao Jammy

Ebenezer E Eshun

Paul Christian Parries

Anil Kumar Chinthakindi

Ricky S Amos

Casey Jon Grant

Keith Edward Downes

John Edward Florkey

Michael C Triplett

Gary L Patton

Patrick Raffin

Jean-Marc Rousseau

Susan E Chaloux

Francis Rodier

Seong-dong Kim

Caroline Aussilhou

Corinne Buchet

Gregory Bazan

Joseph F Kudlacik

Bernard P Leroy

The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

Method of fabricating a precision buried resistor

A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

MOS varactor with segmented gate doping

A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.

Modification of electrical properties for semiconductor wafers

A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

Precision polysilicon resistor process

A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

Method of adjusting resistors post silicide process

A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

Method of forming thermally stable polycrystal to single crystal electrical contact structure

Improved reliability structures containing quantum conductive barrier layer structures are obtained by employing quantum conductive layers in combination with thin regions of amorphous or microcrystalline semiconductor material. The quantum conductive structures are especially useful when incorporated into trench capacitors to reduce or eliminate the occurrence of low temperature fails and single cell fails in DRAM circuits.

Structures containing quantum conductive barrier layers

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Essex Junction, VT, United States of America

Heidi L Greer