Samsung Electronics Co., Ltd.

Hei Seung Kim

Sang Woo Lee

Hyunmog Park

Woo Bin Song

Jongwon Hong

Jinmin Kim

Daehyun Kim

Min Hee Cho

Jongmin Baek

Mirco Cantoro

Junsoo Kim

Insun Park

Chankyung Kim

Minhee Cho

Sangkil Lee

Sangwuk Park

Beomyong Hwang

Jaehong Min

Hyunsik Park

Ho Young Lee

Heeseok Lee

Gilheyun Choi

Jongmyeong Lee

Ho Dong Lee

Soojeoung Park

Kyoung Hee Nam

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

Semiconductor package

Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

Fusion memory device and method of fabricating the same

A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

Method of forming a semiconductor device including an active region with variable atomic concentration of oxide semiconductor material

A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

Semiconductor memory device

A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.

Semiconductor device including active region with variable atomic concentration of oxide semiconductor material and method of forming the same

Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern

Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Electroplating methods for fabricating integrated circuit devices and devices fabricated thereby

Growing community of inventors

Suwon-si, South Korea

Hei Seung Kim