International Business Machines Corporation

Hehching Harry Li

Humberto Felipe Casal

Trong Duc Nguyen

Nandor G Thoma

Joel Roger Davidson

David L Arlington

Steven Lee Gregor

David John Krolak

Bruce G Hazelzet

David M Wu

Patrick F Dutton

Franklin Mark Liu

Bharat J Oza

Campbell H Snyder

Jerry K Radcliffe

A Frank Weaver

Jacqueline M Cole

David Ming-Whei Wu

Jacqueline K Morris

Yuan C Lo

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (&ldquo;PLL&rdquo;) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

System and method for testing a clock signal

A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.

Storage subsystem including an error correcting cache and means for

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Three state phase detector

During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

Controlling power up using clock gating

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

Hierarchical clocking system using adaptive feedback

A system and method for accessing a multiplicity of memory devices connected to a serial bus of defined protocol and which a direct memory device selection range smaller than the number of memory devices. The memory devices are divided among microcontrollers which selectively enable one or more memory devices responsive to higher level addressing signals sent to the microcontrollers. Thereafter, selectively enabled groups of memory devices are accessed by applying the limited addressing range of the serial bus. The invention finds particular use in modularized systems where cost and complexity are significant considerations by extending the normal range of the chip select function to increase the memory device count beyond the standard bus protocol. A preferred embodiment uses EEPROM devices and an I.sup.2 C protocol bus.

Address range extension for a modular computer

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ('PLL') circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

An apparatus and method for polling a plurality of components in a data processing system includes a sensor for determining when a request for power up has been made, a series of parallel circuits extending between a power sequence monitor/power control device and individual computer system components, a configuration bus connected between the system components and the power sequence monitor/power control device and comparison circuitry connected to the configuration bus for comparing a signal sent from the power sequence monitor/power control device, through the configuration bus and system components, and returned to the power sequence monitor/power control device, with a predetermined code for identifying and locating the system components.

Preliminary polling for identification and location of

A 'smart' memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide seminconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the 'smart' memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

Growing community of inventors

Austin, TX, United States of America

Hehching Harry Li