Taiwan Semiconductor Manufacturing Comp. Ltd.

Heh-Chang Huang

Shang-Yun Hou

Sung-Hui Huang

Kuan-Yu Huang

Pei-Haw Tsao

Shyue-Ter Leu

Fu-Jen Li

Yushun Lin

Chen-Hua Douglas Yu

Chi-Hsi Wu

Ying-Ching Shih

Hsien-Pin Hu

Hsing-Kuo Hsia

Chin-Fu Kao

Li-Chung Kuo

Wen-Hsin Wei

Shu-Chia Hsu

Chih-Chieh Hung

Tien-Yu Huang

Yu-Shun Lin

Kung-Chen Yeh

Pai-Yuan Li

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Semiconductor device package having warpage control

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer, wherein a first thickness of the conductive pillar is substantially equal to a sum of a second thickness of the second chip structure and a third thickness of the first conductive bump. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar.

Method for forming chip package structure

Semiconductor device package having warpage control and method of forming the same

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

Semiconductor package, integrated optical communication system

Method of forming a dummy die of an integrated circuit having an embedded annular structure

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.

Chip package structure with dummy bump and method for forming the same

Growing community of inventors

Hsinchu, Taiwan

Heh-Chang Huang