Silicon Laboratories Inc.

Hegong Wei

Kenneth Wilson Fernald

Brian Taylor Brunn

Paul Zavalney

Chester Yu

A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.

Data delay compensator circuit

A signal gating circuit includes a logic circuit that receives a stop signal and an input signal and provides an intermediate signal in response, and a pulse stretcher. The pulse stretcher provides an output signal with no pulse when a width of a pulse of the intermediate signal is less than a first amount, with a pulse having a first pulse width that begins after a start of the pulse of the intermediate signal and ends at a predetermined delay thereafter when a pulse width of the intermediate signal is greater than the first amount but less than a second amount, and with a pulse having a second pulse width that begins after the start of the pulse of the intermediate signal and ends after an end of the pulse of the intermediate signal when a pulse width of the intermediate signal is greater than the second amount.

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Austin, TX, United States of America

Hegong Wei