Samsung Electronics Co., Ltd.

Cj Cheiljedang Corporation

Heeseok Lee

Yonghoon Kim

Junghwa Kim

Kyoungsei Choi

Yunhyeok Im

Seung-Yong Cha

Keung Beum Kim

Yoonha Jung

Hyunjong Moon

Moonseob Jeong

Junso Pak

Jongkook Kim

Youngsang Cho

Bona Baek

Tongsuk Kim

Jangwoo Lee

Heungkyu Kwon

Yun-Hee Lee

Se-Ho You

Chiyoung Lee

Jisoo Hwang

Seung Hwan Kim

Jong-Won Lee

Yunseok Choi

Hyunki Kim

Bina Kim

Byoung Hoon Yoon

Sung Kwang Son

Eunseok Cho

Seon Hye Kim

Hei Seung Kim

Hyojin Yun

Soyoung Lim

Lan Huh

Heejung Choi

Hyuna Kim

Soojeoung Park

Jun So Pak

Hyeryun Yoo

PaLan Lee

Haena Oh

Tai-Hyun Eum

Jangmee Seo

Goun Park

Kyoungkuk Chae

Chunguan Kim

Bongwee Yu

A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

Semiconductor package and method of manufacturing the same

A semiconductor package includes a first interconnection structure, a first semiconductor chip disposed on the first interconnection structure and including a plurality of through-vias and first pads connected to the plurality of through-vias; a second semiconductor chip disposed on the first interconnection structure, including second pads electrically connected to the first pads, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding side surfaces of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having higher thermal conductivity than a thermal conductivity of silicon; and an encapsulant surrounding side surfaces of the heat dissipating structure.

Semiconductor package having improved heat dissipation characteristics

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

Semiconductor package

A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

Semiconductor package including a dualized signal wiring structure

A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

Semiconductor package for improving power integrity characteristics

A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.

Hybrid semiconductor device and electronic device

A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

Semiconductor package including composite molding structure

A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.

Semiconductor package including dual stiffener

A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.

Semiconductor devices including power connection lines

A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.

Semiconductor package and semiconductor device including the same

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Yongin-si, South Korea

Heeseok Lee