Xilinx, Inc.

Heera Nand

David A Knol

Siddharth Rele

Suman Kumar Timmireddy

Nabeel Shirazi

Sonal Santan

Salil Ravindra Raje

Stephen P Rozum

Amit Kasat

Riyas Noorudeen Remla

Bradley K Fross

Sudipto Chakraborty

Yong Li

Fernando J Martinez Vallina

Sahil Goyal

Mahesh Sankroj

Niloy Roy

Brendan Matthew O'Higgins

Rajesh Bansal

Susheel Kumar Puthana

Ethan T Parker

Awdhesh Kumar Sahu

Providing host-to-kernel streaming support can include determining a platform circuitry for use with a streaming kernel of a circuit design. The streaming kernel is configured for implementation in a user circuitry region of an integrated circuit (IC) to perform tasks offloaded from a host computer. The platform circuitry is configured for implementation in a static circuitry region of the IC. The platform circuitry is configured to establish a communication link with the host computer. An adaptable streaming controller can be inserted within the circuit design. The adaptable streaming controller is configured for implementation in the user circuitry region and connects to the streaming kernel. The adaptable streaming controller further communicatively links the streaming kernel with the platform circuitry. The adaptable streaming controller can be parameterized for exchanging data between the platform circuitry and the streaming kernel based, at least in part, on a type of the platform circuitry.

Host-to-kernel streaming support for disparate platforms

Implementing a kernel as circuitry in an integrated circuit can include determining, using a processor, memory access operations and work operations from kernel program code and generating, using the processor, a circuit design from the kernel program code. The circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations.

Architecture for asynchronous memory transfer for kernels implemented in integrated circuits

Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

Configurable system and method for debugging a circuit

Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators

A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

Programmable IC design creation using circuit board data

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Alwar, India

Heera Nand