Motorola Corporation

Heemyong Park

Vida Ilderem

Jenny M Ford

Zhirong Tang

Andreas A Wild

Marco Racanelli

Robert Bruce Davies

Juergen A Foerstner

Wen-Ling M Huang

Hyungcheol Shin

A method for forming an isolation structure ( ) on a SOI substrate ( ) is provided. A three layer stack of an etchant barrier layer ( ), a stress relief layer ( ), and an oxide mask layer ( ) is formed on the SOI substrate ( ). The three layer stack is patterned and etched to expose portions of the etchant barrier layer ( ). The silicon layer ( ) below the exposed portions of the etchant barrier layer ( ) is oxidized to form the isolation structure ( ). The isolation structure ( ) comprises a bird's head region ( ) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure ( ) that leaves the SOI substrate ( ) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

Reduced stress isolation for SOI devices and a method for fabricating

An n-channel device ( ) and a p-channel device ( ) are formed from a single epitaxial silicon layer ( ). During the deposition of the single epitaxial silicon layer ( ), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region ( ), a channel region ( ), and a source region ( ). The dopant concentration is modified during the formation of the channel region ( ) to create a doping profile ( ). The doping profile ( ) has a first profile ( ) that is constant and a second profile ( ) that changes.

Method of manufacturing vertical semiconductor device

An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.

Vertical semiconductor device and method of manufacturing the same

An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Insulated gate semiconductor device

An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

Method of manufacturing an insulated gate semiconductor device having a

Vertical semiconductor device

Insulated gate semiconductor device and method of manufacture

A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

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Gilbert, AZ, United States of America

Heemyong Park