Samsung Electronics Co., Ltd.

Heekwon Park

Yang Seok Ki

Ho Bin Lee

Ilgu Hong

Rekha Pitchumani

Tong Zhang

Marie Mai Nguyen

Changho Choi

Zongwang Li

Jongmin Gim

Jaemin Jung

Mehran Elyasi

Hobin Lee

Yangseok Ki

A hierarchical memory system and method. In some embodiments, the method includes: demoting a first page of data from a fast memory to a slow memory; promoting the first page of data from the slow memory to an intermediate memory zone; and promoting the first page of data from the intermediate memory zone to the fast memory, wherein the intermediate memory zone includes a virtual zone within the slow memory.

Hierarchical memory system

A system and method for page mirroring for storage. In some embodiments, the method includes: reading first data from a persistent memory device; establishing that the first data is stored in a first cache; and copying the first data from the first cache to a system memory, wherein the persistent memory device supports an external protocol and a memory protocol.

System and method for page mirroring for storage

A method includes storing, at a computing device, access granularity criteria associated with a memory area. The method further includes receiving a memory operation request requesting access to a first portion of the memory area at the first access granularity. The method further includes in response to the memory operation request satisfying the access granularity criteria, sending, from the computing device, a command to a storage device based on the memory operation request.

Systems and methods for sending a command to a storage device

A system is disclosed. A storage device may store a data. A load module may read the data from the storage device based at least in part on an input/output (I/O) request. A scheduler may place the I/O request in a queue for delivery to the load module based at least in part on a size of the I/O request being less than a threshold.

Low latency multiple storage device system

A method and redundant array of independent disks (RAID) system are provided. An operation is received from an application at a file system (FS) of the RAID system. A memory mapping module of the RAID system receives at least an FS logical block address (LBA) in accordance with the operation. The memory mapping module creates a mapping from a virtual memory of the application to a RAID array in a system memory of the RAID system using at least the FS LBA.

Method and system for solid state drive (SSD)-based redundant array of independent disks (RAID)

A system is disclosed. A first storage device may supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. A second storage device may also support the cache coherent interconnect protocol. A redundant array of independent disks (RAID) circuit may communicate with the first storage device and the second storage device. The RAID circuit may apply a RAID level to the first storage device and the second storage device. The RAID circuit may be configured to receive a request using the byte level protocol and to access data on the first storage device.

Systems and methods for a redundant array of independent disks (RAID) using a RAID circuit in cache coherent interconnect storage devices

A method for memory allocation may include determining an amount of use for a first memory page, wherein the first memory page is mapped to a first page group of a first group level, a second memory page may be mapped to a second page group of the first group level, and the first memory page and the second memory page may be mapped to a third page group of a second group level, and selecting, based on an allocation request, the first memory page based on the amount of use. The amount of use may include a first amount of use, and the method may further include determining a second amount of use for the second memory page, wherein the first memory page may be selected based on the first amount of use and the second amount of use.

Systems, methods, and apparatus for wear-level aware memory allocation

A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.

Systems, methods, and devices for page relocation for garbage collection

A method may include receiving, from a process, a memory allocation request for a memory system comprising a first channel having a first channel utilization and a second channel having a second channel utilization, selecting, based on the first channel utilization and the second channel utilization, the first channel, and allocating, to the process, a page of memory from the first channel. The selecting may include selecting the first channel based on a balanced random policy. The selecting may include generating a ticket based on a random number and a number of free pages, comparing the ticket to a number of free pages of the first channel, and selecting the first channel based on the comparing. The selecting may include selecting the first channel based on a least used channel policy.

Systems, methods, and devices for utilization aware memory allocation

Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Prefetching operations in storage devices

A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

Systems and methods for a redundant array of independent disks (RAID) using a decoder in cache coherent interconnect storage devices

Provided is a method of linking multiple KV blocks in a KV chain to ensure data consistency, the method including allocating an internal key to both a first KV block and a recovery begin internal key, allocating a next internal key that is different from the internal key and that corresponds to a next KV block, and encapsulating respective user key values in the first KV block and in the next KV block, wherein the first KV block is accessed by reading the recovery begin internal key, and wherein the next KV block is accessed by reading the next internal key of the first KV block.

Reliable key-value store with write-ahead-log-less mechanism

Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

Storage system, method, and apparatus for fast IO on PCIE devices

Provided is a system and method for searching for a target key in a database, the method including populating a hash-offset table of a sorted key table with hash-offset table entries, the hash-offset table entries having a hash-value corresponding to a respective key, and a hash offset, sorting the hash-offset table entries based on the hash-values, searching for a target hash-value of the hash-values corresponding to a target key in the hash-offset table, locating a target key-value pair corresponding to the target key based on the target hash-value, and saving a location of the target key-value pair.

Internal key hash directory in table

Provided is a method of data storage, the method including receiving a write request including a user key, determining the user key exists in a cache, generating or updating metadata corresponding to the user key, writing data corresponding to the write request to a storage device, converting the metadata to a device format corresponding to the storage device, and storing the metadata on the storage device.

Growing community of inventors

Cupertino, CA, United States of America

Heekwon Park