Samsung Electronics Co., Ltd.

Heejun Shim

Hoyoung Kim

Sunmin Kwon

Seonghun Jeong

Kwontaek Kwon

Jae-Young Kim

Sangheon Lee

Yeon-Gon Cho

Scott Mahlke

Jeongae Park

Hyunchul Park

Jinseok Lee

Yongjun Park

Sukjin Kim

SeongHun Jeong

Yenjo Han

Seonghoon Jeong

Summin Kwon

A method and a device for texture filtering include determining an upper mipmap and a lower mipmap based on a level of detail (LOD) value corresponding to a quad, obtaining first color values corresponding to the upper mipmap, obtaining second color values corresponding to the lower mipmap, and obtaining third color values of the pixels of the quad by using linear interpolation, based on the obtained first and second color values.

Method and device for texture filtering

A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

Pipeline processor and an equal model compensator method and apparatus to store the processing result

A method of determining a level of detail (LOD) for a texturing includes: acquiring texture coordinate data on pixels included in an upper block; determining a reference quad among quads included in the upper block; determining a similarity between the determined reference quad and the upper block using texture coordinates of the determined reference quad and the upper block; and determining LODs of remaining quads among the quads included in the upper block to be the same as an LOD of the determined reference quad in response to the determining of the similarity including determining that the determined reference quad and the upper block are similar.

Graphics processing apparatus and method for determining level of detail (LOD) for texturing in graphics pipeline

A cache memory apparatus including a cache memory including a bank, a partition configuration unit configured to divide the cache memory into partitions by allocating the bank to a texture among textures for rendering, and a controller configured to receive a partition ID, of texture data requested by a device that performs the rendering, determine whether the requested texture data is stored in a partition corresponding to the partition ID among the plurality of partitions, and output the requested texture data to the device based on a result of the determination.

Cache memory system for a pixel shader and method of operating the same

Provided is a decompression apparatus and method thereof for decompressing rendering data. The decompression apparatus includes a data parsing unit configured to acquire a control component and a texture component from compressed input data including rendering information of an object, a decompression controller configured to allocate the control component to a control unit, wherein the control unit extracts a control command from the control component, and a logic calculation unit configured to, based on the control command, restore texture data of the object from the texture component.

Apparatus and method of decompressing rendering data and recording medium thereof

Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.

Processor with reconfigurable architecture including a token network simulating processing of processing elements

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Seoul, South Korea

Heejun Shim